December 3, 2021
The Effect of Pattern Loading on BEOL Yield and Reliability during Chemical Mechanical Planarization
CMP (Chemical mechanical planarization) is required during semiconductor processing of many memory and logic devices. CMP is used to create planar surfaces and achieve uniform layer thickness during semiconductor manufacturing, […]
April 17, 2020
Using failure bin classification, yield prediction and process window optimization to predict and enhance yield Device yield is highly dependent upon proper process targeting and variation control of fabrication steps, […]
October 18, 2017
Reducing back-end-of-line (BEOL) interconnect parasitic capacitance remains a focus for advanced technology node development. Porous low-k dielectric materials have been used to achieve reduced capacitance, however, these materials remain fragile […]
May 17, 2017
Until EUV lithography becomes a reality, multiple patterning technologies such as triple litho-etch (LELELE), self-aligned double patterning (SADP), and self-aligned quadruple patterning (SAQP) are being used to meet the stringent […]
April 12, 2017
Things were easy for integrators when the pattern they had on the mask ended up being the pattern they wanted on the chip. Multi-patterning schemes such as Self-Aligned Double Patterning […]
February 13, 2017
At SPIE Advanced Lithography 2017, Coventor Will Present Results of Studies to Increase Density and Yield of Next-Generation Semiconductor Devices CARY, NC– February 13, 2017 – Coventor®, Inc., the leading […]
December 15, 2016
Coventor recently assembled an expert panel at IEDM 2016, to discuss changes to BEOL process technology that would be needed to continue dimensional scaling to 7 nm and lower. We […]
June 14, 2016
IMEC Partner Technical Week Review In March 2016, Coventor was invited to the biannual Partner Technical Week (PTW) at IMEC in Leuven, Belgium. IMEC, a world-leading research group in nanotechnology, […]