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What the Experts Think: Delivering the Next 5 Years of Semiconductor Technology

Posted in: Coventor Blog by Marketing | Comments Off Tuesday, December 19, 2017

Coventor recently sponsored an expert panel discussion at IEDM 2017 to discuss how we might advance the semiconductor industry into the next generation of technology. The panel discussed alternative methods to solve fundamental problems of technology scaling, using advances in semiconductor architectures, patterning, metrology, advanced process control, variation reduction, co-optimization and new integration schemes. Our panel included Rick Gottscho, CTO of Lam Research; Mark Dougherty, vice president of advanced module engineering at GlobalFoundries; David Shortt, technical fellow at KLA-Tencor; Gary Zhang, vice president of computational lithography products at ASML; and Shay Wolfling, CTO of Nova Measuring Instruments.

The Next 5 Years of Semiconductor Technology

L-R: Ed Sperling (moderator), Shay Wolfling, Rick Gottscho, Mark Dougherty, Gary Zhang, David Shortt

Reducing BEOL Parasitic Capacitance using Air Gaps

Posted in: Coventor Blog by Sandra Liu | Comments Off Wednesday, October 18, 2017

By: Michael Hargrove, SP&I Engineer

Reducing back-end-of-line (BEOL) interconnect parasitic capacitance remains a focus for advanced technology node development. Porous low-k dielectric materials have been used to achieve reduced capacitance, however, these materials remain fragile and prone to reliability concerns. More recently, air gap has been successfully incorporated into 14nm technology [1], and numerous schemes have been proposed to create the air gap [2-3]. There are many challenges to integrate air gap in BEOL such as process margin for un-landed vias and overall increased process complexity. In this paper, we introduce virtual fabrication (SEMulator3D^®) as a means to study air gap process integration optimization and resulting interconnect capacitance reduction. Initial calibration to published air gap data is demonstrated. read more…

Tagged air gap, back end of line, BEOL, beol parasitic capacitance, SEMulator3D

What drives SADP BEOL variability?

Posted in: Coventor Blog by Sandra Liu | Comments Off Wednesday, May 17, 2017

By: Michael Hargrove, Semiconductor Process & Integration Engineer

Until EUV lithography becomes a reality, multiple patterning technologies such as triple litho-etch (LELELE), self-aligned double patterning (SADP), and self-aligned quadruple patterning (SAQP) are being used to meet the stringent patterning demands of advanced back-end-of-line (BEOL) technologies. For the 7nm technology node, patterning requirements include a metal pitch of 40nm or less. This narrow pitch requirement forces the use of spacer based pitch multiplication techniques. Unfortunately, these techniques have high process/lithography variability, which can severely impact RC and overall device performance.

Photoresist shape in 3D: Understanding how small variations in photoresist shape significantly impact multi-patterning yield

Posted in: Coventor Blog by Sandra Liu | Comments Off Wednesday, April 12, 2017

By: Mustafa B. Akbulut, Ph.D., Team Lead, Quality Assurance, Semiconductor Solutions

Things were easy for integrators when the pattern they had on the mask ended up being the pattern they wanted on the chip. Multi-patterning schemes such as Self-Aligned Double Patterning (SADP) and Self-Aligned Quadruple Patterning (SAQP) have changed that dramatically. Now, what you have on the mask determines only a part of what you will get at the end. read more…

Tagged BEOL, Coventor, Fin Patterning, multi-patterning, Photolithography, Process Modeling, Process Simulation, Process Variability, SAQP, Self-Aligned Double Patterning, Self-Aligned Quadruple Patterning, Semiconductor Mask, semiconductor process modeling, semiconductor process variation, SEMulator3D, SPIE Advanced Lithography, virtual fabrication

Coventor Unveils New Scientific Findings on Lithography Processing For Improved Semiconductor Scalability and Performance

Posted in: Press Releases by Marketing | Comments Off Monday, February 13, 2017

At SPIE Advanced Lithography 2017, Coventor Will Present Results of Studies to Increase Density and Yield of Next-Generation Semiconductor Devices

CARY, NC– February 13, 2017 – Coventor®, Inc., the leading supplier of virtual fabrication solutions for semiconductor devices and micro-electromechanical systems (MEMS), will present findings from its research on advanced semiconductor fabrication processes at SPIE Advanced Lithography 2017. The results of these studies provide insight into techniques for advancing the state-of-the-art in semiconductor technology through use of new and emerging photomask, lithography and process technologies. read more…

Tagged 7 nm, BEOL, Coventor, ETCH, EUV, imec, lithography, multi-patterning, Process Development, Process Modeling, Process Simulation, Process Variability, SAQP, Self-Aligned Quadruple Patterning, semiconductor process modeling, semiconductor process variation, SEMulator3D, virtual fabrication

BEOL Barricades: Navigating Future Yield, Reliability and Cost Challenges

Posted in: Coventor Blog by Marketing | Comments Off Thursday, December 15, 2016

By: David Fried, Ph.D., Chief Technology Officer, Semiconductor

Coventor recently assembled an expert panel at IEDM 2016, to discuss changes to BEOL process technology that would be needed to continue dimensional scaling to 7 nm and lower. We asked our panelists questions such as: read more…

Tagged 3D architecture, 5NM, 7 nm, Air Gap technology, BEOL, Coventor, Dielectric, EUV, interconnect, LOW-K DIELECTRICS, nanowires, patterning, Process Integration, RC DELAY, SAQP, Self-Aligned Quadruple Patterning

IMEC Partner Technical Week Review

Posted in: Coventor Blog by Marketing | Comments Off Tuesday, June 14, 2016

IMEC Partner Technical Week Review

By: Aurélie Juncker, Semiconductor Process & Integration Engineer

a. Fully aligned Via with Cu recess approach – Gayle Murdoch, b. STT-RAM – Davide Crotti, c. N10 Supernova2 process – Matt Gallagher

In March 2016, Coventor was invited to the biannual Partner Technical Week (PTW) at IMEC in Leuven, Belgium. IMEC, a world-leading research group in nanotechnology, organizes their Partner Technical Week every 6 months to present scientific results to their partners. During this week, a number of specialists from IMEC’s many partner companies also discuss their progress in areas related to IMEC’s research. This event brings together a large number of engineers who are specialists in their domain, and provides an interesting forum to leverage the scientific knowledge gained by IMEC and its partners. read more…

Tagged 7 nm, BEOL, Coventor, DOE, DUV, ETCH, EUV, FEOL, i193, lithography, misalignment, multi-patterning, N7, patterning, virtual fabrication

Inside Process Technology

Posted in: Press Coverage by Admin | Comments Off Tuesday, May 10, 2016

By Mark Lapedus

Semiconductor Engineering sat down to discuss the foundry business, memory, process technology, lithography and other topics with David Fried, chief technology officer at Coventor, a supplier of predictive modeling tools. What follows are excerpts of that conversation.

SE: Chipmakers are ramping up 16nm/14nm finFETs today, with 10nm and 7nm finFETs just around the corner. What do you see happening at these advanced nodes, particularly at 7nm?

Fried: Most people are predicting evolutionary scaling from 14nm to 10nm to 7nm. It’s doubtful that we will see anything really earth-shattering in these technologies. And so, a lot of the challenges come down to patterning. We are going to see multi-patterning schemes really take hold at more levels. For example, the fins are now based on self-aligned double patterning. People will move into self-aligned quad patterning. The gates are maybe self-aligned double. Now, they will move into self-aligned quad. So, that’s going to be a big expense, because each level is going to have multiple passes and multiple cuts.

read the full article here

Tagged 10NM, 3D NAND, 5NM, ATOMIC-LEVEL VARIABILITY, BEOL, Coventor, DEPOSITION, Directed Self Assembly, DSA, ETCH, EUV, III-V MATERIALS, INTEL, lithography, LOW-K DIELECTRICS, MRAM, multi-patterning, NANOWIRE FETS, RC DELAY, RERAM, SADP, TSMC

BEOL

What the Experts Think: Delivering the Next 5 Years of Semiconductor Technology

Reducing BEOL Parasitic Capacitance using Air Gaps

What drives SADP BEOL variability?

Photoresist shape in 3D: Understanding how small variations in photoresist shape significantly impact multi-patterning yield

Coventor Unveils New Scientific Findings on Lithography Processing For Improved Semiconductor Scalability and Performance

BEOL Barricades: Navigating Future Yield, Reliability and Cost Challenges

IMEC Partner Technical Week Review

Inside Process Technology

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