April 26, 2022
Figure 2: Schematic view of standard CMOS including an electro-mechanical switch monolithically integrated into BEOL [2].   Courtesy:  University of California, Berkeley

There is Plenty of Room at the Top: Imagining Miniaturized Electro-Mechanical Switches in Low-Power Computing Applications

The First Computers:  Electro-Mechanical Computing The first computers were built using electro-mechanical components, unlike today’s modern electronic systems. Alain Turing’s cryptanalysis multiplier and Konrad Zuse’s  Z2 were invented and built […]
April 15, 2022
Figure 1:  Two different metal line connection designs under consideration

Accelerating Semiconductor Module Development using Shared Process Libraries

One of the fastest ways to predict semiconductor manufacturing final results is by adding together the results of performing individual process steps. Unfortunately, this prediction might ignore critical defects that […]
March 14, 2022
Figure 2: A semi-damascene process flow for BEOL device integration using the new mask set

BEOL integration for the 1.5nm node and beyond

Introduction As we approach the 1.5nm node and beyond, new BEOL device integration challenges will be presented.  These challenges include the need for smaller metal pitches, along with support for […]
December 3, 2021

The Effect of Pattern Loading on BEOL Yield and Reliability during Chemical Mechanical Planarization

CMP (Chemical mechanical planarization) is required during semiconductor processing of many memory and logic devices.  CMP is used to create planar surfaces and achieve uniform layer thickness during semiconductor manufacturing, […]
April 17, 2020
Fig.1. Bin illustration (a) Pass, (b) HR, (c) VML, (d) MML, (e) VMO, (f) VMS.

Identifying and Preventing Process Failures at 7nm

Using failure bin classification, yield prediction and process window optimization to predict and enhance yield Device yield is highly dependent upon proper process targeting and variation control of fabrication steps, […]
October 18, 2017
SEMulator3D created air gap process flows based on published reports.

Reducing BEOL Parasitic Capacitance using Air Gaps

Reducing back-end-of-line (BEOL) interconnect parasitic capacitance remains a focus for advanced technology node development. Porous low-k dielectric materials have been used to achieve reduced capacitance, however, these materials remain fragile […]
May 17, 2017

What drives SADP BEOL variability?

Until EUV lithography becomes a reality, multiple patterning technologies such as triple litho-etch (LELELE), self-aligned double patterning (SADP), and self-aligned quadruple patterning (SAQP) are being used to meet the stringent […]
April 12, 2017

Photoresist shape in 3D: Understanding how small variations in photoresist shape significantly impact multi-patterning yield

Things were easy for integrators when the pattern they had on the mask ended up being the pattern they wanted on the chip. Multi-patterning schemes such as Self-Aligned Double Patterning […]
February 13, 2017

Coventor Unveils New Scientific Findings on Lithography Processing For Improved Semiconductor Scalability and Performance

At SPIE Advanced Lithography 2017, Coventor Will Present Results of Studies to Increase Density and Yield of Next-Generation Semiconductor Devices CARY, NC– February 13, 2017 – Coventor®, Inc., the leading […]
December 15, 2016

BEOL Barricades: Navigating Future Yield, Reliability and Cost Challenges

Coventor recently assembled an expert panel at IEDM 2016, to discuss changes to BEOL process technology that would be needed to continue dimensional scaling to 7 nm and lower. We […]
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