At the beginning of my career in semiconductor equipment, the backside of the wafer was a source of anxiety. In one memorable instance in my early career, several wafers flew […]
Introduction BEOL metal line RC delay has become a dominant factor that limits chip performance at advanced nodes [1]. Smaller metal line pitches require a narrower line CD and line-to-line […]
The First Computers: Electro-Mechanical Computing The first computers were built using electro-mechanical components, unlike today’s modern electronic systems. Alain Turing’s cryptanalysis multiplier and Konrad Zuse’s Z2 were invented and built […]
One of the fastest ways to predict semiconductor manufacturing final results is by adding together the results of performing individual process steps. Unfortunately, this prediction might ignore critical defects that […]
Introduction As we approach the 1.5nm node and beyond, new BEOL device integration challenges will be presented. These challenges include the need for smaller metal pitches, along with support for […]
CMP (Chemical mechanical planarization) is required during semiconductor processing of many memory and logic devices. CMP is used to create planar surfaces and achieve uniform layer thickness during semiconductor manufacturing, […]
Using failure bin classification, yield prediction and process window optimization to predict and enhance yield Device yield is highly dependent upon proper process targeting and variation control of fabrication steps, […]
Reducing back-end-of-line (BEOL) interconnect parasitic capacitance remains a focus for advanced technology node development. Porous low-k dielectric materials have been used to achieve reduced capacitance, however, these materials remain fragile […]
Until EUV lithography becomes a reality, multiple patterning technologies such as triple litho-etch (LELELE), self-aligned double patterning (SADP), and self-aligned quadruple patterning (SAQP) are being used to meet the stringent […]
Things were easy for integrators when the pattern they had on the mask ended up being the pattern they wanted on the chip. Multi-patterning schemes such as Self-Aligned Double Patterning […]