Challenges and Solutions for Silicon Wafer Bevel Defects during 3D NAND Flash Manufacturing

By: Pradeep Nanja, Software Applications Engineer


As semiconductor technology scales down in size, process integration complexity and defects are increasing in 3D NAND flash, partially due to larger stack deposits and thickness variability between the wafer center and the wafer edge. Industry participants are working to reduce defect density at the wafer edge to improve overall wafer yield. Attention has focused on common wafer bevel defects such as peeling (or delamination), particle contamination, arcing, and micromasking to improve yield. We will now review these defects in detail and discuss ways to prevent them. read more…

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