December 3, 2021

The Effect of Pattern Loading on BEOL Yield and Reliability during Chemical Mechanical Planarization

CMP (Chemical mechanical planarization) is required during semiconductor processing of many memory and logic devices.  CMP is used to create planar surfaces and achieve uniform layer thickness during semiconductor manufacturing, […]
May 21, 2019

Challenges and Solutions for Silicon Wafer Bevel Defects during 3D NAND Flash Manufacturing

As semiconductor technology scales down in size, process integration complexity and defects are increasing in 3D NAND flash, partially due to larger stack deposits and thickness variability between the wafer […]
January 15, 2019
Y-branch structure (SiO2 upper and lower claddings not shown)

Analyzing Worst-Case Silicon Photonic Device Performance Through Process Modeling and Optical Simulation

This blog is a summary of a technical paper given at an SPIE Photonics conference. Read the full paper here. Background Silicon photonics is an emerging and rapidly-expanding design platform […]
August 8, 2017
Example test photonic IC, with common elements such as waveguides, grating coupler, MZI, photodetector and fill pattern.

Silicon Photonics: Solving Process Variation and Manufacturing Challenges

As silicon photonics manufacturing gains momentum with additional foundry and 300mm offerings, process variation issues are coming to light. Variability in silicon processing affects the waveguide shape and can result […]
March 12, 2015
Example of a 3D NAND flash memory array.

Defect Evolution in 3D NAND Flash

3D NAND Flash has become a hot topic in non-volatile memory these days. While planar NAND flash is still going strong, it has been increasingly difficult to scale planar technology […]
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