March 14, 2022
Figure 2: A semi-damascene process flow for BEOL device integration using the new mask set

BEOL integration for the 1.5nm node and beyond

Introduction As we approach the 1.5nm node and beyond, new BEOL device integration challenges will be presented.  These challenges include the need for smaller metal pitches, along with support for […]
February 11, 2022
Figure 3: DEDED Contour, Level Plot and Output Structure of DOE2

Accelerating Semiconductor Process Development Using Virtual Design of Experiments

Design of Experiments (DOE) is a powerful concept in semiconductor engineering research and development.   DOEs are sets of experiments used to explore the sensitivity of experimental variables and their effect […]
October 27, 2021

Using Process Modeling to Enhance Device Uniformity during Self-Aligned Quadruple Patterning

Despite the growing interest in EUV lithography, self-aligned quadruple patterning (SAQP) still holds many technical advantages in pattern consistency, simplicity, and cost.  This is particularly true for very simple and […]
May 27, 2021
Figure 2. Simulation results displaying 3 different etch processes followed by 4 different deposition processes

Using Virtual Process Libraries to Improve Semiconductor Manufacturing

People think that semiconductor process simulation libraries should be developed using a perfect theoretical background that is strongly supported by empirical data. This might be true in academic research, where […]
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