By Mark Lapedus
Semiconductor Engineering sat down to discuss the foundry business, memory, process technology, lithography and other topics with David Fried, chief technology officer at Coventor, a supplier of predictive modeling tools. What follows are excerpts of that conversation.
SE: Chipmakers are ramping up 16nm/14nm finFETs today, with 10nm and 7nm finFETs just around the corner. What do you see happening at these advanced nodes, particularly at 7nm?
Fried: Most people are predicting evolutionary scaling from 14nm to 10nm to 7nm. It’s doubtful that we will see anything really earth-shattering in these technologies. And so, a lot of the challenges come down to patterning. We are going to see multi-patterning schemes really take hold at more levels. For example, the fins are now based on self-aligned double patterning. People will move into self-aligned quad patterning. The gates are maybe self-aligned double. Now, they will move into self-aligned quad. So, that’s going to be a big expense, because each level is going to have multiple passes and multiple cuts.
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Tagged 10NM, 3D NAND, 5NM, ATOMIC-LEVEL VARIABILITY, BEOL, Coventor, DEPOSITION, Directed Self Assembly, DSA, ETCH, EUV, III-V MATERIALS, INTEL, lithography, LOW-K DIELECTRICS, MRAM, multi-patterning, NANOWIRE FETS, RC DELAY, RERAM, SADP, TSMC
By: Mattan Kamon, PhD., Distinguished Technologist, R&D, Coventor
But first, more generally, will directed self-assembly (DSA) join Extreme Ultraviolet (EUV) Lithography and next generation multi-patterning techniques to pattern the next memory and logic technologies? Appealing to the wisdom of crowds, the organizers of the 2015 1st International DSA symposium recently surveyed the attendees, and nearly 75% believed DSA would insert into high volume manufacturing within the next 5 years, and nearly 30% predicted insertion within the next 2 years. What is gating insertion? The crowd rated defectivity as the most critical issue facing DSA. This fact adds weight to memory being the first to be patterned with DSA. This is because, as Roel Gronheid from IMEC pointed out last month at the SPIE Advanced Lithography conference , memory chips can tolerate single failing cells through redundancy and so can could tolerate higher defectivity in patterning (roughly 1 defect/cm2 compared to 0.01 defect/cm2 for logic). Defectivity rates for DSA aren’t there yet (according to public information), but are rapidly approaching , . read more…
Tagged 14 nm DRAM process modeling, Directed Self Assembly, DSA, LER, LWR, Process Modeling, Process Simulation, SAQP, Self-Aligned Quadruple Patterning, semiconductor process modeling, Semiconductor Process Simulation, virtual fabrication
By Jeff Dorsch
The annual SPIE Advanced Lithography symposium in San Jose, Calif., hasn’t offered a clear winner in the next-generation lithography race. It’s becoming clearer, however, that 193i immersion and extreme-ultraviolet lithography will co-exist in the future, while directed self-assembly, nanoimprint lithography, and maybe even electron-beam direct-write technology will fit into the picture, too.
At the same time, plasma deposition and etching processes are assuming a greater interdependence with 193i, especially when it comes to multiple patterning, such as self-aligned double patterning, self-aligned quadruple patterning, and self-aligned octuple patterning (yes, there is such a thing!).
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Tagged 193 immersion, ASML Holding, Coventor, Directed Self Assembly, DSA, EUV, GLOBALFOUNDRIES, INTEL, lithography, multiple patterning, nanoimprint, nanoimprint lithography, plasma deposition, SPIE, SST News, TOPPAN PHOTOMASKS, TSMC