May 30, 2023
Figure 1 displays a single cell of a conventional DRAM that consists of 2 Word Lines (WLs), a Bit Line (BL) and 2 Storage Node Contacts (SNC) in Figure 1(a). There are 3 images in the figure. The Saddle Fin is produced during the WL etch step (prior to WL metal deposition) and is located below the cell wordline (Figure 1(b), right center inside a yellow dotted circle). The Saddle Fin structure can be seen in detail by making a vertical cut in the wordline direction (Fig.1(b), right). During device simulation, the Saddle Fin performance can be measured by virtually cropping a transistor and adding ports at the Gate, Source and Drain after an SNC Process (Fig.1(c), showing the gate, source and drain).
Published by Tae Yeon Oh at May 30, 2023
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Improving DRAM Device Performance Through Saddle Fin Process Optimization

As DRAM technology nodes have scaled down, access transistor issues have been highlighted due to weak gate controllability. Saddle Fins with Buried Channel Array Transistors (BCAT) have subsequently been introduced […]
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December 19, 2022
Figure 2. Backside power delivery using buried power rails, based on [2] (not to scale).
Published by Sandy Wen at December 19, 2022
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The Other Side of the Wafer: The Latest Developments in Backside Power Delivery

At the beginning of my career in semiconductor equipment, the backside of the wafer was a source of anxiety. In one memorable instance in my early career, several wafers flew […]
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December 7, 2022
Published by Jack Lapidas at December 7, 2022
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SEMICON Korea 2023

Benjamin Vincent, Ph.D. will be giving a presentation entitled “Virtual Technology Development of A New 3D-DRAM Architecture”
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September 22, 2022
Figure 2. Virtual metrology results for minimum and maximum area.
Published by QingPeng Wang at September 22, 2022
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Pathfinding by process window modeling: Advanced DRAM capacitor patterning process window evaluation using virtual fabrication

With continuous device scaling, process windows have become narrower and narrower due to smaller feature sizes and greater process step variability [1]. A key task during the R&D stage of […]
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November 16, 2021
Figure 2.Cutaway of buried wordline spanning saddle-fin transistors.
Published by Sandy Wen at November 16, 2021
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Understanding Electrical Line Resistance at Advanced Semiconductor Nodes

When evaluating shrinking metal linewidths in advanced semiconductor devices, bulk resistivity is not the sole materials property for deriving electrical resistance. At smaller line dimensions, local resistivity is dominated by […]
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December 14, 2020
  Figure 2:  SEMulator3D identifies device electrodes in a 3D structure and simulates device characteristics similar to TCAD software, but without the need for time-consuming TCAD modeling.
Published by Daebin Yim at December 14, 2020
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Process Window Optimization of DRAM by Virtual Fabrication

New integration and patterning schemes used in 3D memory and logic devices have created manufacturing and yield challenges.  Industrial focus has shifted from the scaling of predictable unit processes in […]
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October 23, 2020
Fig. 6: Channel leakage profile from the fin surface to the fin center at different sidewall angle splits.
Published by QingPeng Wang at October 23, 2020
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Micro Loading and its Impact on Device Performance: A Wiggling Active Area Case in an Advanced DRAM Process

In a DRAM structure, the charging and discharging process of capacitor-based memory cells is directly controlled by the transistor [1].With transistor sizes approaching the lower limits of physical achievability, manufacturing […]
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January 29, 2020
Fig. 1 (a) DRAM Memory Cell, (b) GIDL in Cell Transistor, (c) Dielectric leakage between BLC and SNC, (d) Dielectric leakage at DRAM Capacitor
Published by Tae Yeon Oh at January 29, 2020
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Identifying DRAM Failures Caused by Leakage Current and Parasitic Capacitance

Leakage current has been a leading cause of device failure in DRAM design, starting with the 20nm technology node. Problems with leakage current in DRAM design can lead to reliability […]
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