December 14, 2020
  Figure 2:  SEMulator3D identifies device electrodes in a 3D structure and simulates device characteristics similar to TCAD software, but without the need for time-consuming TCAD modeling.
Published by Daebin Yim at December 14, 2020
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Process Window Optimization of DRAM by Virtual Fabrication

New integration and patterning schemes used in 3D memory and logic devices have created manufacturing and yield challenges.  Industrial focus has shifted from the scaling of predictable unit processes in […]
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October 23, 2020
Fig. 6: Channel leakage profile from the fin surface to the fin center at different sidewall angle splits.
Published by QingPeng Wang at October 23, 2020
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Micro Loading and its Impact on Device Performance: A Wiggling Active Area Case in an Advanced DRAM Process

In a DRAM structure, the charging and discharging process of capacitor-based memory cells is directly controlled by the transistor [1].With transistor sizes approaching the lower limits of physical achievability, manufacturing […]
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January 29, 2020
Fig. 1 (a) DRAM Memory Cell, (b) GIDL in Cell Transistor, (c) Dielectric leakage between BLC and SNC, (d) Dielectric leakage at DRAM Capacitor
Published by Tae Yeon Oh at January 29, 2020
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Identifying DRAM Failures Caused by Leakage Current and Parasitic Capacitance

Leakage current has been a leading cause of device failure in DRAM design, starting with the 20nm technology node. Problems with leakage current in DRAM design can lead to reliability […]
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