December 19, 2022
![Figure 2. Backside power delivery using buried power rails, based on [2] (not to scale).](https://www.coventor.com/wp-content/uploads/2022/12/Figure-2-December-2022-Coventor-website-blog-from-Sandy-Wen-960x720.png)
At the beginning of my career in semiconductor equipment, the backside of the wafer was a source of anxiety. In one memorable instance in my early career, several wafers flew […]
December 7, 2022
Benjamin Vincent, Ph.D. will be giving a presentation entitled “Virtual Technology Development of A New 3D-DRAM Architecture”
September 22, 2022
With continuous device scaling, process windows have become narrower and narrower due to smaller feature sizes and greater process step variability [1]. A key task during the R&D stage of […]
November 16, 2021
When evaluating shrinking metal linewidths in advanced semiconductor devices, bulk resistivity is not the sole materials property for deriving electrical resistance. At smaller line dimensions, local resistivity is dominated by […]
December 14, 2020
New integration and patterning schemes used in 3D memory and logic devices have created manufacturing and yield challenges. Industrial focus has shifted from the scaling of predictable unit processes in […]
October 23, 2020
In a DRAM structure, the charging and discharging process of capacitor-based memory cells is directly controlled by the transistor [1].With transistor sizes approaching the lower limits of physical achievability, manufacturing […]
June 29, 2020
The very first all-electronic memory was the Williams-Kilburn tube, developed in 1947 at Manchester University. It used a cathode ray tube to store bits as dots on the screen’s surface. […]
January 29, 2020
Leakage current has been a leading cause of device failure in DRAM design, starting with the 20nm technology node. Problems with leakage current in DRAM design can lead to reliability […]