February 11, 2022
Design of Experiments (DOE) is a powerful concept in semiconductor engineering research and development. DOEs are sets of experiments used to explore the sensitivity of experimental variables and their effect […]
March 8, 2021
Static Random-Access Memory (SRAM) has been a key element for logic circuitry since the early age of the semiconductor industry. The SRAM cell usually consists of six transistors connected to […]
October 23, 2020
In a DRAM structure, the charging and discharging process of capacitor-based memory cells is directly controlled by the transistor [1].With transistor sizes approaching the lower limits of physical achievability, manufacturing […]
May 26, 2020
UNDERSTANDING THE BENEFITS AND CHALLENGES OF A NEW, NEXT-GENERATION SEMICONDUCTOR ARCHITECTURE In our November 2019 blog [1], we discussed using virtual fabrication (SEMulator3D®) to benchmark different process integration options for […]
March 21, 2019
Advanced logic scaling has created some difficult technical challenges, including a requirement for highly dense patterning. Imec recently confronted this challenge, by working toward the use of Metal 2 (M2) […]
April 13, 2018
Yield and cost have always been critical factors for both manufacturers and designers of semiconductor products. It is a continuous challenge to meet targets of both yield and cost, due […]
September 21, 2016
Yield and cost have always been critical factors for both manufacturers and designers of semiconductor products. Meeting yield and product cost targets is a continuous challenge, due to new device […]
June 9, 2015
DAC 2015 is in full swing in San Francisco this week, and Coventor is there again. But this year, we’re also doing a special joint demonstration with Silicon Cloud International. […]