August 18, 2022
Figure 2: (a) Layout design, (b) Top view of a typical metal line generated, (c) cross sectional view of the metal line, (d) LER status of RMS and Correlation length split.

How does Line Edge Roughness (LER) affect Semiconductor Performance at Advanced Nodes ?

Introduction BEOL metal line RC delay has become a dominant factor that limits chip performance at advanced nodes [1]. Smaller metal line pitches require a narrower line CD and line-to-line […]
April 15, 2022
Figure 1:  Two different metal line connection designs under consideration

Accelerating Semiconductor Module Development using Shared Process Libraries

One of the fastest ways to predict semiconductor manufacturing final results is by adding together the results of performing individual process steps. Unfortunately, this prediction might ignore critical defects that […]
March 14, 2022
Figure 2: A semi-damascene process flow for BEOL device integration using the new mask set

BEOL integration for the 1.5nm node and beyond

Introduction As we approach the 1.5nm node and beyond, new BEOL device integration challenges will be presented.  These challenges include the need for smaller metal pitches, along with support for […]
November 16, 2021
Figure 2.Cutaway of buried wordline spanning saddle-fin transistors.

Understanding Electrical Line Resistance at Advanced Semiconductor Nodes

When evaluating shrinking metal linewidths in advanced semiconductor devices, bulk resistivity is not the sole materials property for deriving electrical resistance. At smaller line dimensions, local resistivity is dominated by […]
May 27, 2021
Figure 2. Simulation results displaying 3 different etch processes followed by 4 different deposition processes

Using Virtual Process Libraries to Improve Semiconductor Manufacturing

People think that semiconductor process simulation libraries should be developed using a perfect theoretical background that is strongly supported by empirical data. This might be true in academic research, where […]
September 23, 2020
Fig 5: ALD thickness dependence and layer etch. Using profiled anisotropic etching of the SiO2 (blue) and SiN (green), the resulting hole shape can be determined using varying ALD thicknesses. The best shape is found at a 23.5 nm ALD value, using a Semulator 3D visibility etch model that was previously validated again actual etch results.

Accelerating the Development of Dry Etch Processes during Feature Dependent Etch

In dry etching, the trajectory of accelerated ions is non-uniform and non-vertical, due to collisions with gas molecules and other random thermal effects (Figure 1). This has an impact on […]
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