April 13, 2023
Introduction In logic devices such as FinFETs (field-effect transistors), metal gate parasitic capacitance can negatively impact electrical performance. One way to reduce this parasitic capacitance is to optimize the metal […]
November 8, 2022
Introduction The semiconductor industry has been focused on scaling and developing advanced technologies using advanced etch tools and techniques. With decreasing semiconductor device dimensions and increases in process complexity, the […]
August 18, 2022
Introduction BEOL metal line RC delay has become a dominant factor that limits chip performance at advanced nodes [1]. Smaller metal line pitches require a narrower line CD and line-to-line […]
April 15, 2022
One of the fastest ways to predict semiconductor manufacturing final results is by adding together the results of performing individual process steps. Unfortunately, this prediction might ignore critical defects that […]
March 14, 2022
Introduction As we approach the 1.5nm node and beyond, new BEOL device integration challenges will be presented. These challenges include the need for smaller metal pitches, along with support for […]
November 16, 2021
When evaluating shrinking metal linewidths in advanced semiconductor devices, bulk resistivity is not the sole materials property for deriving electrical resistance. At smaller line dimensions, local resistivity is dominated by […]
May 27, 2021
People think that semiconductor process simulation libraries should be developed using a perfect theoretical background that is strongly supported by empirical data. This might be true in academic research, where […]
September 23, 2020
In dry etching, the trajectory of accelerated ions is non-uniform and non-vertical, due to collisions with gas molecules and other random thermal effects (Figure 1). This has an impact on […]