April 13, 2023
Introduction In logic devices such as FinFETs (field-effect transistors), metal gate parasitic capacitance can negatively impact electrical performance. One way to reduce this parasitic capacitance is to optimize the metal […]
October 27, 2022
Reducing the parasitic capacitance between the gate metal and the source/drain contact of a transistor can decrease device switching delays. One way to reduce parasitic capacitance is to reduce the […]
September 20, 2019
As the need to scale transistors to ever-smaller sizes continues to press on technology designers, the impact of parasitic resistance and capacitance can approach or even outpace other aspects of […]
July 31, 2019
Driven by Moore’s law, memory and logic semiconductor manufacturers pursue higher transistor density to improve product cost and performance [1]. In NAND Flash technologies, this has led to the market […]
April 12, 2017
Things were easy for integrators when the pattern they had on the mask ended up being the pattern they wanted on the chip. Multi-patterning schemes such as Self-Aligned Double Patterning […]
June 14, 2016
IMEC Partner Technical Week Review In March 2016, Coventor was invited to the biannual Partner Technical Week (PTW) at IMEC in Leuven, Belgium. IMEC, a world-leading research group in nanotechnology, […]