September 20, 2019
Figure 6 Capacitance components and capacitance variance compared to different epi thicknesses

How FinFET Device Performance is Affected by Epitaxial Process Variations

As the need to scale transistors to ever-smaller sizes continues to press on technology designers, the impact of parasitic resistance and capacitance can approach or even outpace other aspects of […]
July 31, 2019
Top view of slit and channel hole at different nodes

Advanced Patterning Techniques for 3D NAND Devices

Driven by Moore’s law, memory and logic semiconductor manufacturers pursue higher transistor density to improve product cost and performance [1]. In NAND Flash technologies, this has led to the market […]
September 19, 2017
FinFET Process Step Illustration

Using Advanced Statistical Analysis to improve FinFET transistor performance

Trial and error wafer fabrication is commonly used to study the effect of process changes in the development of FinFET and other advanced semiconductor technologies. Due to the interaction of upstream […]
April 12, 2017

Photoresist shape in 3D: Understanding how small variations in photoresist shape significantly impact multi-patterning yield

Things were easy for integrators when the pattern they had on the mask ended up being the pattern they wanted on the chip. Multi-patterning schemes such as Self-Aligned Double Patterning […]
June 14, 2016
a. Fully aligned Via with Cu recess approach - Gayle Murdoch, b. STT-RAM - Davide Crotti, c. N10 Supernova2 process - Matt Gallagher

IMEC Partner Technical Week Review

IMEC Partner Technical Week Review In March 2016, Coventor was invited to the biannual Partner Technical Week (PTW) at IMEC in Leuven, Belgium. IMEC, a world-leading research group in nanotechnology, […]
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