By: Benjamin Vincent, Ph.D., Staff Engineer, Semiconductor Process & Integration
Engineering decisions are always data-driven. As scientists, we only believe in facts and not in intuition or feelings.
At the manufacturing stage, the semiconductor industry is eager to provide data and facts to engineers based upon metrics such as the quantity of wafers produced per hour and sites/devices tested on each of those wafers. The massive quantity of data generated in semiconductor manufacturing can provide facts that engineers can use to make immediate and accurate decisions, such as how they might correct any excursion or yield drift. Data exists, so life is (kind of…) easy! read more…
Tagged 2018 SPIE Advanced Lithography Conference, 5 nm, 5 nm Semiconductor Node, FSAV, Fully Self-Aligned Via, imec, Patterning Yield, SAB, SAQP, Self-Aligned Blocks, Self-Aligned Quadruple Patterning, SEMulator3D
At SPIE Advanced Lithography 2017, Coventor Will Present Results of Studies to Increase Density and Yield of Next-Generation Semiconductor Devices
CARY, NC– February 13, 2017 – Coventor®, Inc., the leading supplier of virtual fabrication solutions for semiconductor devices and micro-electromechanical systems (MEMS), will present findings from its research on advanced semiconductor fabrication processes at SPIE Advanced Lithography 2017. The results of these studies provide insight into techniques for advancing the state-of-the-art in semiconductor technology through use of new and emerging photomask, lithography and process technologies. read more…
Tagged 7 nm, BEOL, Coventor, ETCH, EUV, imec, lithography, multi-patterning, Process Development, Process Modeling, Process Simulation, Process Variability, SAQP, Self-Aligned Quadruple Patterning, semiconductor process modeling, semiconductor process variation, SEMulator3D, virtual fabrication
By Scotten Jones, SemiWiki
On Tuesday evening December 8th at IEDM, Coventor held a panel discussion entitled the “The Last Half Nanometer”. Coventor is a leading provider of simulation software used to design processes. This is my third year attending the Coventor panel discussion at IEDM and they are always excellent with very strong panels and discussion. The panel was made up of David Fried CTO of Coventor, Alek Chen from ASML, Aaron Theon of IMEC, and Subramanian Iyer from UCLA. Subramanian acted as both a panelist and the moderator.
read the full article here
Tagged ASML, Coventor, DSA, EUV, imec, Moore's Law, multi-patterning, Process Modeling, Process Variability, semiconductor process modeling, semiconductor process variation
By Luke Collins, Tech Design Forum
New variability issues highlighted by a massive process simulation exercise could make it more difficult than expected to achieve the performance advantages of emerging 7nm and 5nm processes.
Nano-electronics research centre imec has worked with Coventor to simulate the process variability of its 7nm BEOL fabrication processes using Coventor’s SEMulator3D virtual fabrication platform. The simulation of a full process window, looking at how multiple parameters of multiple processes interact, would have taken one million wafers to complete using conventional methods.
read the full article here
• Joint development team leverages SEMulator3D to explore semiconductor process variation issues at unprecedented levels
• Collaboration team has conducted a massive computer modeling simulation of a million
wafers to explore process variability in 7nm BEOL semiconductor fabrication
• The extending collaboration aims to further advance the availability, yield and cost of
manufacturing processes for the next generation of 7 nm semiconductor products
Leuven, Belgium & Cary, North Carolina, United States – December 7, 2015 – Imec, a
world-leading nanoelectronics research center and Coventor, a leading supplier of semiconductor process development tools, today announced the expansion of a joint development project to explore process variation issues in 7nm semiconductor technology. read more…
Tagged 7 nm, 7 nm semiconductor, 7 nm semiconductor manufacturing, 7nm BEOL, Coventor, imec, Process Modeling, semiconductor process, semiconductor process modeling, semiconductor process variation, SEMulator3D