September 22, 2022
Figure 2. Virtual metrology results for minimum and maximum area.

Pathfinding by process window modeling: Advanced DRAM capacitor patterning process window evaluation using virtual fabrication

With continuous device scaling, process windows have become narrower and narrower due to smaller feature sizes and greater process step variability [1]. A key task during the R&D stage of […]
August 18, 2022
Figure 2: (a) Layout design, (b) Top view of a typical metal line generated, (c) cross sectional view of the metal line, (d) LER status of RMS and Correlation length split.

How does Line Edge Roughness (LER) affect Semiconductor Performance at Advanced Nodes ?

Introduction BEOL metal line RC delay has become a dominant factor that limits chip performance at advanced nodes [1]. Smaller metal line pitches require a narrower line CD and line-to-line […]
December 3, 2021

The Effect of Pattern Loading on BEOL Yield and Reliability during Chemical Mechanical Planarization

CMP (Chemical mechanical planarization) is required during semiconductor processing of many memory and logic devices.  CMP is used to create planar surfaces and achieve uniform layer thickness during semiconductor manufacturing, […]
October 27, 2021

Using Process Modeling to Enhance Device Uniformity during Self-Aligned Quadruple Patterning

Despite the growing interest in EUV lithography, self-aligned quadruple patterning (SAQP) still holds many technical advantages in pattern consistency, simplicity, and cost.  This is particularly true for very simple and […]
April 17, 2020
Fig.1. Bin illustration (a) Pass, (b) HR, (c) VML, (d) MML, (e) VMO, (f) VMS.

Identifying and Preventing Process Failures at 7nm

Using failure bin classification, yield prediction and process window optimization to predict and enhance yield Device yield is highly dependent upon proper process targeting and variation control of fabrication steps, […]
March 24, 2020

Exploring the Impact of EUV Resist Thickness on Via Patterning Uniformity using a Litho/Etch Modeling Platform

Via patterning at advanced nodes requires extremely low critical dimension (CD) values, typically below 30nm. Controlling these dimensions is a serious challenge, since there are many inherent sources of variation […]
July 31, 2019
Top view of slit and channel hole at different nodes

Advanced Patterning Techniques for 3D NAND Devices

Driven by Moore’s law, memory and logic semiconductor manufacturers pursue higher transistor density to improve product cost and performance [1]. In NAND Flash technologies, this has led to the market […]
June 25, 2019
Lam Semiconductor Equipment

Controlling Variability using Semiconductor Process Window Optimization

To ensure success in semiconductor technology development, process engineers must set the allowed ranges for wafer process parameters. Variability must be controlled, so that final fabricated devices meet required specifications. […]
March 21, 2019
Composite of Virtual SAQP Model with Actual Si Cross-Section Data (animation)

Improving SAQP Patterning Yield using Virtual Fabrication and Advanced Process Control

Advanced logic scaling has created some difficult technical challenges,  including a requirement for highly dense patterning. Imec recently confronted this challenge, by working toward the use of Metal 2 (M2) […]
March 21, 2018

Improving Patterning Yield at the 5 nm Semiconductor Node

Engineering decisions are always data-driven.  As scientists, we only believe in facts and not in intuition or feelings. At the manufacturing stage, the semiconductor industry is eager to provide data […]
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