April 17, 2020
Fig.1. Bin illustration (a) Pass, (b) HR, (c) VML, (d) MML, (e) VMO, (f) VMS.

Identifying and Preventing Process Failures at 7nm

Using failure bin classification, yield prediction and process window optimization to predict and enhance yield Device yield is highly dependent upon proper process targeting and variation control of fabrication steps, […]
March 24, 2020

Exploring the Impact of EUV Resist Thickness on Via Patterning Uniformity using a Litho/Etch Modeling Platform

Via patterning at advanced nodes requires extremely low critical dimension (CD) values, typically below 30nm. Controlling these dimensions is a serious challenge, since there are many inherent sources of variation […]
July 31, 2019
Top view of slit and channel hole at different nodes

Advanced Patterning Techniques for 3D NAND Devices

Driven by Moore’s law, memory and logic semiconductor manufacturers pursue higher transistor density to improve product cost and performance [1]. In NAND Flash technologies, this has led to the market […]
June 25, 2019
Lam Semiconductor Equipment

Controlling Variability using Semiconductor Process Window Optimization

To ensure success in semiconductor technology development, process engineers must set the allowed ranges for wafer process parameters. Variability must be controlled, so that final fabricated devices meet required specifications. […]
March 21, 2019
Composite of Virtual SAQP Model with Actual Si Cross-Section Data (animation)

Improving SAQP Patterning Yield using Virtual Fabrication and Advanced Process Control

Advanced logic scaling has created some difficult technical challenges,  including a requirement for highly dense patterning. Imec recently confronted this challenge, by working toward the use of Metal 2 (M2) […]
March 21, 2018

Improving Patterning Yield at the 5 nm Semiconductor Node

Engineering decisions are always data-driven.  As scientists, we only believe in facts and not in intuition or feelings. At the manufacturing stage, the semiconductor industry is eager to provide data […]
February 28, 2018
New in SEMulator3D 7.0: Powerful new process and device simulation capabilities

Coventor Adds Device Analysis Capabilities to SEMulator3D 7.0

New Features Enable SEMulator3D Version 7.0 to Address Both Process Modeling and Device Analysis for Better Insight into Advanced Semiconductor Technology Development CARY, NC– February 28, 2018 – February 26, […]
December 19, 2017
2017 IEDM Panel Speakers on Stage

What the Experts Think: Delivering the Next 5 Years of Semiconductor Technology

Coventor recently sponsored an expert panel discussion at IEDM 2017 to discuss how we might advance the semiconductor industry into the next generation of technology.  The panel discussed alternative methods […]
May 17, 2017

What drives SADP BEOL variability?

Until EUV lithography becomes a reality, multiple patterning technologies such as triple litho-etch (LELELE), self-aligned double patterning (SADP), and self-aligned quadruple patterning (SAQP) are being used to meet the stringent […]
April 12, 2017

Photoresist shape in 3D: Understanding how small variations in photoresist shape significantly impact multi-patterning yield

Things were easy for integrators when the pattern they had on the mask ended up being the pattern they wanted on the chip. Multi-patterning schemes such as Self-Aligned Double Patterning […]
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