February 28, 2018

Coventor Adds Device Analysis Capabilities to SEMulator3D 7.0

New Features Enable SEMulator3D Version 7.0 to Address Both Process Modeling and Device Analysis for Better Insight into Advanced Semiconductor Technology Development CARY, NC– February 28, 2018 – February 26, […]
December 19, 2017

What the Experts Think: Delivering the Next 5 Years of Semiconductor Technology

Coventor recently sponsored an expert panel discussion at IEDM 2017 to discuss how we might advance the semiconductor industry into the next generation of technology.  The panel discussed alternative methods […]
May 17, 2017

What drives SADP BEOL variability?

Until EUV lithography becomes a reality, multiple patterning technologies such as triple litho-etch (LELELE), self-aligned double patterning (SADP), and self-aligned quadruple patterning (SAQP) are being used to meet the stringent […]
April 12, 2017

Photoresist shape in 3D: Understanding how small variations in photoresist shape significantly impact multi-patterning yield

Things were easy for integrators when the pattern they had on the mask ended up being the pattern they wanted on the chip. Multi-patterning schemes such as Self-Aligned Double Patterning […]
February 13, 2017

Coventor Unveils New Scientific Findings on Lithography Processing For Improved Semiconductor Scalability and Performance

At SPIE Advanced Lithography 2017, Coventor Will Present Results of Studies to Increase Density and Yield of Next-Generation Semiconductor Devices CARY, NC– February 13, 2017 – Coventor®, Inc., the leading […]
December 15, 2016

BEOL Barricades: Navigating Future Yield, Reliability and Cost Challenges

Coventor recently assembled an expert panel at IEDM 2016, to discuss changes to BEOL process technology that would be needed to continue dimensional scaling to 7 nm and lower. We […]
September 21, 2016

Design Process Technology Co-Optimization for Manufacturability

Yield and cost have always been critical factors for both manufacturers and designers of semiconductor products.   Meeting yield and product cost targets is a continuous challenge, due to new device […]
June 14, 2016

IMEC Partner Technical Week Review

IMEC Partner Technical Week Review In March 2016, Coventor was invited to the biannual Partner Technical Week (PTW) at IMEC in Leuven, Belgium. IMEC, a world-leading research group in nanotechnology, […]
March 17, 2016

Will directed self-assembly pattern 14nm DRAM?

But first, more generally, will directed self-assembly (DSA) join Extreme Ultraviolet (EUV) Lithography and next generation multi-patterning techniques to pattern the next memory and logic technologies?  Appealing to the wisdom […]
February 8, 2016

Coventor to Showcase Lithography Research at SPIE 2016

CARY, NC– February 8, 2016 – Coventor®, Inc., the leading supplier of virtual fabrication solutions for semiconductor devices and micro-electromechanical systems (MEMS), today announced it will be exhibiting at the […]