December 15, 2016

BEOL Barricades: Navigating Future Yield, Reliability and Cost Challenges

Coventor recently assembled an expert panel at IEDM 2016, to discuss changes to BEOL process technology that would be needed to continue dimensional scaling to 7 nm and lower. We […]
September 21, 2016
3D DTCO Process in SEMulator3D

Design Process Technology Co-Optimization for Manufacturability

Yield and cost have always been critical factors for both manufacturers and designers of semiconductor products.   Meeting yield and product cost targets is a continuous challenge, due to new device […]
June 14, 2016
a. Fully aligned Via with Cu recess approach - Gayle Murdoch, b. STT-RAM - Davide Crotti, c. N10 Supernova2 process - Matt Gallagher

IMEC Partner Technical Week Review

IMEC Partner Technical Week Review In March 2016, Coventor was invited to the biannual Partner Technical Week (PTW) at IMEC in Leuven, Belgium. IMEC, a world-leading research group in nanotechnology, […]
March 17, 2016

Will directed self-assembly pattern 14nm DRAM?

But first, more generally, will directed self-assembly (DSA) join Extreme Ultraviolet (EUV) Lithography and next generation multi-patterning techniques to pattern the next memory and logic technologies?  Appealing to the wisdom […]
February 8, 2016

Coventor to Showcase Lithography Research at SPIE 2016

CARY, NC– February 8, 2016 – Coventor®, Inc., the leading supplier of virtual fabrication solutions for semiconductor devices and micro-electromechanical systems (MEMS), today announced it will be exhibiting at the […]
January 28, 2016

Advanced Lithography and Process Variation Modeling Using SEMulator3D

One of the top and probably toughest challenges that process integrators are facing today in a silicon fab is process variability. As a former process integrator working hard to ramp […]
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