New in SEMulator3D 7.0: Powerful new process and device simulation capabilities
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Coventor Adds Device Analysis Capabilities to SEMulator3D 7.0
New Features Enable SEMulator3D Version 7.0 to Address Both Process Modeling and Device Analysis for Better Insight into Advanced Semiconductor Technology Development
CARY, NC– February 28, 2018 – February 26, 2018 – Coventor, Inc., a Lam Research Company, the leading supplier of design automation solutions for semiconductor devices and micro-electromechanical systems (MEMS), today announced the availability of SEMulator3D® 7.0 – the newest version of its semiconductor virtual fabrication platform. With added features, performance improvements, and a new Device Analysis capability, SEMulator3D 7.0 addresses both process and device simulation while lowering the barriers to advanced semiconductor technology development. The new Device Analysis capability enables seamless understanding of how process changes, process variability, and integration schemes directly impact transistor device performance. read more…
Tagged 3D NAND, Coventor, device analysis, FinFET, FinFET Technology, FinFET transistor performance, lithography, lithography modeling, multi-patterning, NAND, Netlist, Netlist Extraction, Press release, Process Development, Process Integration, Process Modeling, Process Simulation, Process Variability, Process variation, semiconductor patterning, semiconductor process flow, semiconductor process modeling, semiconductor process variation, SEMulator 3D, SEMulator3D, SPICE simulation, TCAD, transistor device performance, transistor IV curves, transistor performance, virtual fabrication
Coventor recently sponsored an expert panel discussion at IEDM 2017 to discuss how we might advance the semiconductor industry into the next generation of technology. The panel discussed alternative methods to solve fundamental problems of technology scaling, using advances in semiconductor architectures, patterning, metrology, advanced process control, variation reduction, co-optimization and new integration schemes. Our panel included Rick Gottscho, CTO of Lam Research; Mark Dougherty, vice president of advanced module engineering at GlobalFoundries; David Shortt, technical fellow at KLA-Tencor; Gary Zhang, vice president of computational lithography products at ASML; and Shay Wolfling, CTO of Nova Measuring Instruments.
L-R: Ed Sperling (moderator), Shay Wolfling, Rick Gottscho, Mark Dougherty, Gary Zhang, David Shortt
Tagged 10NM, 2NM, 3D NAND, 3D XPOINT, 3NM, 5NM, 7NM, ASML, BEOL, DRAM, ETCH, EUV, FINFETS, GATE-ALL-AROUND FETS, GLOBALFOUNDRIES, INSPECTION, KLA-TENCOR, LAM RESEARCH, lithography, METROLOGY, Moore's Law, MRAM, NANOSHEETS, NOVA MEASURING INSTRUMENTS, PHASE-CHANGE MEMORY, RERAM, RESISTANCE, STRESS, STT-RAM, THIN FILMS, VON NEUMANN ARCHITECTURE
At SPIE Advanced Lithography 2017, Coventor Will Present Results of Studies to Increase Density and Yield of Next-Generation Semiconductor Devices
CARY, NC– February 13, 2017 – Coventor®, Inc., the leading supplier of virtual fabrication solutions for semiconductor devices and micro-electromechanical systems (MEMS), will present findings from its research on advanced semiconductor fabrication processes at SPIE Advanced Lithography 2017. The results of these studies provide insight into techniques for advancing the state-of-the-art in semiconductor technology through use of new and emerging photomask, lithography and process technologies. read more…
Tagged 7 nm, BEOL, Coventor, ETCH, EUV, imec, lithography, multi-patterning, Process Development, Process Modeling, Process Simulation, Process Variability, SAQP, Self-Aligned Quadruple Patterning, semiconductor process modeling, semiconductor process variation, SEMulator3D, virtual fabrication
By: Dalong Zhao – Semiconductor Process & Integration Engineering
Yield and cost have always been critical factors for both manufacturers and designers of semiconductor products. Meeting yield and product cost targets is a continuous challenge, due to new device structures and increasingly complex process innovations introduced to achieve improved product performance at each new technology node. Design for manufacturability (DFM) and design process technology co-optimization (DTCO) are widely used techniques that can ensure the successful delivery of both new processes and products in semiconductor manufacturing. In this article, we will discuss how 3D (3 dimensional) DTCO can be used to improve product yield and accelerate product delivery dates in semiconductor manufacturing. read more…
Tagged Coventor, Design Rule Checks, Design Technology Co-Optimization, DRC, DTCO, hotspot, lithography, multi-patterning, Process Development, Process Modeling, Process Simulation, semiconductor process modeling, semiconductor process variation, SEMulator3D
IMEC Partner Technical Week Review
By: Aurélie Juncker, Semiconductor Process & Integration Engineer
a. Fully aligned Via with Cu recess approach – Gayle Murdoch, b. STT-RAM – Davide Crotti, c. N10 Supernova2 process – Matt Gallagher
In March 2016, Coventor was invited to the biannual Partner Technical Week (PTW) at IMEC in Leuven, Belgium. IMEC, a world-leading research group in nanotechnology, organizes their Partner Technical Week every 6 months to present scientific results to their partners. During this week, a number of specialists from IMEC’s many partner companies also discuss their progress in areas related to IMEC’s research. This event brings together a large number of engineers who are specialists in their domain, and provides an interesting forum to leverage the scientific knowledge gained by IMEC and its partners. read more…
Tagged 7 nm, BEOL, Coventor, DOE, DUV, ETCH, EUV, FEOL, i193, lithography, misalignment, multi-patterning, N7, patterning, virtual fabrication
By Mark Lapedus
Semiconductor Engineering sat down to discuss the foundry business, memory, process technology, lithography and other topics with David Fried, chief technology officer at Coventor, a supplier of predictive modeling tools. What follows are excerpts of that conversation.
SE: Chipmakers are ramping up 16nm/14nm finFETs today, with 10nm and 7nm finFETs just around the corner. What do you see happening at these advanced nodes, particularly at 7nm?
Fried: Most people are predicting evolutionary scaling from 14nm to 10nm to 7nm. It’s doubtful that we will see anything really earth-shattering in these technologies. And so, a lot of the challenges come down to patterning. We are going to see multi-patterning schemes really take hold at more levels. For example, the fins are now based on self-aligned double patterning. People will move into self-aligned quad patterning. The gates are maybe self-aligned double. Now, they will move into self-aligned quad. So, that’s going to be a big expense, because each level is going to have multiple passes and multiple cuts.
read the full article here
Tagged 10NM, 3D NAND, 5NM, ATOMIC-LEVEL VARIABILITY, BEOL, Coventor, DEPOSITION, Directed Self Assembly, DSA, ETCH, EUV, III-V MATERIALS, INTEL, lithography, LOW-K DIELECTRICS, MRAM, multi-patterning, NANOWIRE FETS, RC DELAY, RERAM, SADP, TSMC
By Jeff Dorsch
The annual SPIE Advanced Lithography symposium in San Jose, Calif., hasn’t offered a clear winner in the next-generation lithography race. It’s becoming clearer, however, that 193i immersion and extreme-ultraviolet lithography will co-exist in the future, while directed self-assembly, nanoimprint lithography, and maybe even electron-beam direct-write technology will fit into the picture, too.
At the same time, plasma deposition and etching processes are assuming a greater interdependence with 193i, especially when it comes to multiple patterning, such as self-aligned double patterning, self-aligned quadruple patterning, and self-aligned octuple patterning (yes, there is such a thing!).
read the full article here
Tagged 193 immersion, ASML Holding, Coventor, Directed Self Assembly, DSA, EUV, GLOBALFOUNDRIES, INTEL, lithography, multiple patterning, nanoimprint, nanoimprint lithography, plasma deposition, SPIE, SST News, TOPPAN PHOTOMASKS, TSMC