By: David Fried, Ph.D., Chief Technology Officer, Semiconductor
Coventor recently assembled an expert panel at IEDM 2016, to discuss changes to BEOL process technology that would be needed to continue dimensional scaling to 7 nm and lower. We asked our panelists questions such as: read more…
Tagged 3D architecture, 5NM, 7 nm, Air Gap technology, BEOL, Coventor, Dielectric, EUV, interconnect, LOW-K DIELECTRICS, nanowires, patterning, Process Integration, RC DELAY, SAQP, Self-Aligned Quadruple Patterning
By Mark Lapedus
Semiconductor Engineering sat down to discuss the foundry business, memory, process technology, lithography and other topics with David Fried, chief technology officer at Coventor, a supplier of predictive modeling tools. What follows are excerpts of that conversation.
SE: Chipmakers are ramping up 16nm/14nm finFETs today, with 10nm and 7nm finFETs just around the corner. What do you see happening at these advanced nodes, particularly at 7nm?
Fried: Most people are predicting evolutionary scaling from 14nm to 10nm to 7nm. It’s doubtful that we will see anything really earth-shattering in these technologies. And so, a lot of the challenges come down to patterning. We are going to see multi-patterning schemes really take hold at more levels. For example, the fins are now based on self-aligned double patterning. People will move into self-aligned quad patterning. The gates are maybe self-aligned double. Now, they will move into self-aligned quad. So, that’s going to be a big expense, because each level is going to have multiple passes and multiple cuts.
read the full article here
Tagged 10NM, 3D NAND, 5NM, ATOMIC-LEVEL VARIABILITY, BEOL, Coventor, DEPOSITION, Directed Self Assembly, DSA, ETCH, EUV, III-V MATERIALS, INTEL, lithography, LOW-K DIELECTRICS, MRAM, multi-patterning, NANOWIRE FETS, RC DELAY, RERAM, SADP, TSMC