August 19, 2021
Figure 2: A test structure designed to calculate capacitance using 2 nets. The 2 separate nets have 6 ports (P1-P6) and 4 ports (P7-P10), respectively.
Published by Pradeep Nanja at August 19, 2021
Categories

Performing High Accuracy Capacitance Analysis using SEMulator3D

Netlist Extraction is an important SEMulator3D® capability that allows a user to extract parasitic resistance and capacitance for different line and via segments during process modeling. This detailed electrical netlist […]
Do you like it?
Read more - Performing High Accuracy Capacitance Analysis using SEMulator3D
February 22, 2021
Fig. 1. Key process steps comparison of the three structures.
Published by Assawer Soussou at February 22, 2021
Categories

The future of FinFETs at 5nm and beyond: Using combined process and circuit modeling to estimate the performance of the next generation of semiconductors

While contact gate pitch (GP) and fin pitch (FP) scaling continues to provide higher performance and lower power to FinFET platforms, controlling RC parasitics and achieving higher transistor performance at […]
Do you like it?
Read more - The future of FinFETs at 5nm and beyond: Using combined process and circuit modeling to estimate the performance of the next generation of semiconductors