February 11, 2022
Figure 3: DEDED Contour, Level Plot and Output Structure of DOE2

Accelerating Semiconductor Process Development Using Virtual Design of Experiments

Design of Experiments (DOE) is a powerful concept in semiconductor engineering research and development.   DOEs are sets of experiments used to explore the sensitivity of experimental variables and their effect […]
December 3, 2021

The Effect of Pattern Loading on BEOL Yield and Reliability during Chemical Mechanical Planarization

CMP (Chemical mechanical planarization) is required during semiconductor processing of many memory and logic devices.  CMP is used to create planar surfaces and achieve uniform layer thickness during semiconductor manufacturing, […]
November 16, 2021
Figure 2.Cutaway of buried wordline spanning saddle-fin transistors.

Understanding Electrical Line Resistance at Advanced Semiconductor Nodes

When evaluating shrinking metal linewidths in advanced semiconductor devices, bulk resistivity is not the sole materials property for deriving electrical resistance. At smaller line dimensions, local resistivity is dominated by […]
October 27, 2021

Using Process Modeling to Enhance Device Uniformity during Self-Aligned Quadruple Patterning

Despite the growing interest in EUV lithography, self-aligned quadruple patterning (SAQP) still holds many technical advantages in pattern consistency, simplicity, and cost.  This is particularly true for very simple and […]
September 14, 2021
Fig. 3: Leakage current distribution from different directions.

Evaluating the Impact of STI Recess Profile Control on Advanced FinFET Device Performance Using Virtual Fabrication

Profile variation is one of the most important problems during semiconductor device manufacturing and scaling.  These variations can degrade both chip yield and device performance.   Virtual fabrication can be used […]
June 16, 2021
Figure 3: On/off-state current distribution at fin bottom (top figures: no residue; bottom figure: with residue).

Using a Virtual DOE to Predict Process Windows and Device Performance of Advanced FinFET Technology

Introduction With continuing FinFET device process scaling, micro loading control becomes increasingly important due to its significant impact on yield and device performance [1-2]. Micro-loading occurs when the local etch […]
May 27, 2021
Figure 2. Simulation results displaying 3 different etch processes followed by 4 different deposition processes

Using Virtual Process Libraries to Improve Semiconductor Manufacturing

People think that semiconductor process simulation libraries should be developed using a perfect theoretical background that is strongly supported by empirical data. This might be true in academic research, where […]
February 22, 2021
Fig. 1. Key process steps comparison of the three structures.

The future of FinFETs at 5nm and beyond: Using combined process and circuit modeling to estimate the performance of the next generation of semiconductors

While contact gate pitch (GP) and fin pitch (FP) scaling continues to provide higher performance and lower power to FinFET platforms, controlling RC parasitics and achieving higher transistor performance at […]
December 14, 2020
  Figure 2:  SEMulator3D identifies device electrodes in a 3D structure and simulates device characteristics similar to TCAD software, but without the need for time-consuming TCAD modeling.

Process Window Optimization of DRAM by Virtual Fabrication

New integration and patterning schemes used in 3D memory and logic devices have created manufacturing and yield challenges.  Industrial focus has shifted from the scaling of predictable unit processes in […]
June 29, 2020

Semiconductor Memory Evolution and Current Challenges

The very first all-electronic memory was the Williams-Kilburn tube, developed in 1947 at Manchester University. It used a cathode ray tube to store bits as dots on the screen’s surface. […]
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