June 16, 2021
Figure 3: On/off-state current distribution at fin bottom (top figures: no residue; bottom figure: with residue).

Using a Virtual DOE to Predict Process Windows and Device Performance of Advanced FinFET Technology

Introduction With continuing FinFET device process scaling, micro loading control becomes increasingly important due to its significant impact on yield and device performance [1-2]. Micro-loading occurs when the local etch […]
December 14, 2020
  Figure 2:  SEMulator3D identifies device electrodes in a 3D structure and simulates device characteristics similar to TCAD software, but without the need for time-consuming TCAD modeling.

Process Window Optimization of DRAM by Virtual Fabrication

New integration and patterning schemes used in 3D memory and logic devices have created manufacturing and yield challenges.  Industrial focus has shifted from the scaling of predictable unit processes in […]
April 17, 2020
Fig.1. Bin illustration (a) Pass, (b) HR, (c) VML, (d) MML, (e) VMO, (f) VMS.

Identifying and Preventing Process Failures at 7nm

Using failure bin classification, yield prediction and process window optimization to predict and enhance yield Device yield is highly dependent upon proper process targeting and variation control of fabrication steps, […]
June 25, 2019
Lam Semiconductor Equipment

Controlling Variability using Semiconductor Process Window Optimization

To ensure success in semiconductor technology development, process engineers must set the allowed ranges for wafer process parameters. Variability must be controlled, so that final fabricated devices meet required specifications. […]
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