September 22, 2022
Figure 2. Virtual metrology results for minimum and maximum area.
Published by QingPeng Wang at September 22, 2022
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Pathfinding by process window modeling: Advanced DRAM capacitor patterning process window evaluation using virtual fabrication

With continuous device scaling, process windows have become narrower and narrower due to smaller feature sizes and greater process step variability [1]. A key task during the R&D stage of […]
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October 27, 2021
Published by Timothy Yang at October 27, 2021
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Using Process Modeling to Enhance Device Uniformity during Self-Aligned Quadruple Patterning

Despite the growing interest in EUV lithography, self-aligned quadruple patterning (SAQP) still holds many technical advantages in pattern consistency, simplicity, and cost.  This is particularly true for very simple and […]
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July 21, 2020
Figure 4: SEMulator3D model of the Spacer 1 Oxide Fin CD after PMC.   The oxide spacer is turquoise, and the red etch stop layer is amorphous silicon. TEM image with the SEMulator3D image aligned to show visual comparison. Note that sidewall angle and line to line measurements can be used with Process Model Calibration to tune for the deformation caused by the mandrel removal.  
Published by Pradeep Nanja at July 21, 2020
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Process Model Calibration: The Key to Building Predictive and Accurate 3D Process Models

Process engineers and integrators can use virtual process modeling to test alternative process schemes and architectures without relying on wafer-based testing. One important aspect of building an accurate process model […]
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Read more - Process Model Calibration: The Key to Building Predictive and Accurate 3D Process Models