By: Benjamin Vincent, Ph.D., Staff Engineer, Semiconductor Process & Integration
Engineering decisions are always data-driven. As scientists, we only believe in facts and not in intuition or feelings.
At the manufacturing stage, the semiconductor industry is eager to provide data and facts to engineers based upon metrics such as the quantity of wafers produced per hour and sites/devices tested on each of those wafers. The massive quantity of data generated in semiconductor manufacturing can provide facts that engineers can use to make immediate and accurate decisions, such as how they might correct any excursion or yield drift. Data exists, so life is (kind of…) easy! read more…
Tagged 2018 SPIE Advanced Lithography Conference, 5 nm, 5 nm Semiconductor Node, FSAV, Fully Self-Aligned Via, imec, Patterning Yield, SAB, SAQP, Self-Aligned Blocks, Self-Aligned Quadruple Patterning, SEMulator3D
By: Mustafa B. Akbulut, Ph.D., Team Lead, Quality Assurance, Semiconductor Solutions
Things were easy for integrators when the pattern they had on the mask ended up being the pattern they wanted on the chip. Multi-patterning schemes such as Self-Aligned Double Patterning (SADP) and Self-Aligned Quadruple Patterning (SAQP) have changed that dramatically. Now, what you have on the mask determines only a part of what you will get at the end. read more…
Tagged BEOL, Coventor, Fin Patterning, multi-patterning, Photolithography, Process Modeling, Process Simulation, Process Variability, SAQP, Self-Aligned Double Patterning, Self-Aligned Quadruple Patterning, Semiconductor Mask, semiconductor process modeling, semiconductor process variation, SEMulator3D, SPIE Advanced Lithography, virtual fabrication
At SPIE Advanced Lithography 2017, Coventor Will Present Results of Studies to Increase Density and Yield of Next-Generation Semiconductor Devices
CARY, NC– February 13, 2017 – Coventor®, Inc., the leading supplier of virtual fabrication solutions for semiconductor devices and micro-electromechanical systems (MEMS), will present findings from its research on advanced semiconductor fabrication processes at SPIE Advanced Lithography 2017. The results of these studies provide insight into techniques for advancing the state-of-the-art in semiconductor technology through use of new and emerging photomask, lithography and process technologies. read more…
Tagged 7 nm, BEOL, Coventor, ETCH, EUV, imec, lithography, multi-patterning, Process Development, Process Modeling, Process Simulation, Process Variability, SAQP, Self-Aligned Quadruple Patterning, semiconductor process modeling, semiconductor process variation, SEMulator3D, virtual fabrication
By: David Fried, Ph.D., Chief Technology Officer, Semiconductor
Coventor recently assembled an expert panel at IEDM 2016, to discuss changes to BEOL process technology that would be needed to continue dimensional scaling to 7 nm and lower. We asked our panelists questions such as: read more…
Tagged 3D architecture, 5NM, 7 nm, Air Gap technology, BEOL, Coventor, Dielectric, EUV, interconnect, LOW-K DIELECTRICS, nanowires, patterning, Process Integration, RC DELAY, SAQP, Self-Aligned Quadruple Patterning
By: Mattan Kamon, PhD., Distinguished Technologist, R&D, Coventor
But first, more generally, will directed self-assembly (DSA) join Extreme Ultraviolet (EUV) Lithography and next generation multi-patterning techniques to pattern the next memory and logic technologies? Appealing to the wisdom of crowds, the organizers of the 2015 1st International DSA symposium recently surveyed the attendees, and nearly 75% believed DSA would insert into high volume manufacturing within the next 5 years, and nearly 30% predicted insertion within the next 2 years. What is gating insertion? The crowd rated defectivity as the most critical issue facing DSA. This fact adds weight to memory being the first to be patterned with DSA. This is because, as Roel Gronheid from IMEC pointed out last month at the SPIE Advanced Lithography conference , memory chips can tolerate single failing cells through redundancy and so can could tolerate higher defectivity in patterning (roughly 1 defect/cm2 compared to 0.01 defect/cm2 for logic). Defectivity rates for DSA aren’t there yet (according to public information), but are rapidly approaching , . read more…
Tagged 14 nm DRAM process modeling, Directed Self Assembly, DSA, LER, LWR, Process Modeling, Process Simulation, SAQP, Self-Aligned Quadruple Patterning, semiconductor process modeling, Semiconductor Process Simulation, virtual fabrication
By Luke Collins, Tech Design Forum
Directed self assembly (DSA) techniques may offer similar advantages in terms of process variation control as EUV lithography, according to a study carried out using 3D behavioral process modeling techniques.
This could reduce fab cycle times, ease process integration and save costs in advanced semiconductor processes, especially for DRAMs, whose regular structures are well-suited to the use of DSA.
read the full article here