semiconductor process variation

Coventor Adds Device Analysis Capabilities to SEMulator3D 7.0

New in SEMulator3D 7.0:  Powerful new process and device simulation capabilities


For Immediate Distribution
For more information, contact:
Toni Sottak
(408) 876-4418,

 Coventor Adds Device Analysis Capabilities to SEMulator3D 7.0

New Features Enable SEMulator3D Version 7.0 to Address Both Process Modeling and Device Analysis for Better Insight into Advanced Semiconductor Technology Development

CARY, NC– February 28, 2018 – February 26, 2018 – Coventor, Inc., a Lam Research Company, the leading supplier of design automation solutions for semiconductor devices and micro-electromechanical systems (MEMS), today announced the availability of SEMulator3D® 7.0 – the newest version of its semiconductor virtual fabrication platform. With added features, performance improvements, and a new Device Analysis capability, SEMulator3D 7.0 addresses both process and device simulation while lowering the barriers to advanced semiconductor technology development.  The new Device Analysis capability enables seamless understanding of how process changes, process variability, and integration schemes directly impact transistor device performance.   read more…

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What drives SADP BEOL variability?

By: Michael Hargrove, Semiconductor Process & Integration Engineer

Until EUV lithography becomes a reality, multiple patterning technologies such as triple litho-etch (LELELE), self-aligned double patterning (SADP), and self-aligned quadruple patterning (SAQP) are being used to meet the stringent patterning demands of advanced back-end-of-line (BEOL) technologies.  For the 7nm technology node, patterning requirements include a metal pitch of 40nm or less. This narrow pitch requirement forces the use of spacer based pitch multiplication techniques. Unfortunately, these techniques have high process/lithography variability, which can severely impact RC and overall device performance.

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Photoresist shape in 3D: Understanding how small variations in photoresist shape significantly impact multi-patterning yield

By: Mustafa B. Akbulut, Ph.D., Team Lead, Quality Assurance, Semiconductor Solutions

Things were easy for integrators when the pattern they had on the mask ended up being the pattern they wanted on the chip. Multi-patterning schemes such as Self-Aligned Double Patterning (SADP) and Self-Aligned Quadruple Patterning (SAQP) have changed that dramatically. Now, what you have on the mask determines only a part of what you will get at the end. read more…

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AIM Photonics Welcomes Coventor as Newest Member





For Immediate Release: March 16, 2017

Laura Magee (ESD) | | (716) 846-8239 | (800) 260-7313
ESD Press Office | | (800) 260-7313
Steve Ference (AIM) | | 518-956-7319

CUS-Backed Initiative Taps Process Modeling Specialist to Enable Manufacturing of High-Yield, High-Performance Integrated Photonic Designs

Today’s Announcement Builds On Progress Of Finger Lakes Forward, The Region’s Award-Winning Strategic Plan To Generate Robust Economic Growth And Community Development

ROCHESTER, NY and CARY, NCThe American Institute for Manufacturing Integrated Photonics (AIM Photonics), a public-private partnership advancing the nation’s photonics manufacturing capabilities, and Coventor®, Inc., a semiconductor process modeling software company, today announced Coventor as the newest member of AIM Photonics. Coventor will provide access to its unique, physics-driven 3D modeling technology to improve the performance and manufacturability of complex, integrated photonic designs. read more…

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Coventor Unveils New Scientific Findings on Lithography Processing For Improved Semiconductor Scalability and Performance


At SPIE Advanced Lithography 2017, Coventor Will Present Results of Studies to Increase Density and Yield of Next-Generation Semiconductor Devices

CARY, NC– February 13, 2017 – Coventor®, Inc., the leading supplier of virtual fabrication solutions for semiconductor devices and micro-electromechanical systems (MEMS), will present findings from its research on advanced semiconductor fabrication processes at SPIE Advanced Lithography 2017. The results of these studies provide insight into techniques for advancing the state-of-the-art in semiconductor technology through use of new and emerging photomask, lithography and process technologies. read more…

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The Value of Integrating Process Models with TCAD Simulation (and some tips on how to do it)

By: Shi Hao (Jacky) Huang, PhD, Semiconductor Process & Integration Engineer

Coventor January 2017 Blog Graphic

Coventor January 2017 Blog Graphic 2





Nowadays, novel semiconductor technologies have brought complex process flows to the fab.   These process flows are needed to support the manufacturing of advanced 3D semiconductor structures. It can be helpful to model process flows, and their effect on a novel device, prior to physical fabrication.

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Achieving the Vision of Silicon Photonics Processing

By: Sandy Wen, MSEE, Semiconductor Process and Integration Engineer, Coventor

Silicon Photonics Test Die

Silicon Photonics Test Die

With the increasing need for faster data transfer rates, the transition from electrical to optical signaling in data processing is inevitable.   Copper cabling cannot keep up with the upcoming data center bandwidth requirements, for applications such as multimedia streaming and high performance computing.  One technology that could enable true optical communication is silicon photonics. read more…

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Design Process Technology Co-Optimization for Manufacturability

By:   Dalong Zhao – Semiconductor Process & Integration Engineering

Yield and cost have always been critical factors for both manufacturers and designers of semiconductor products.   Meeting yield and product cost targets is a continuous challenge, due to new device structures and increasingly complex process innovations introduced to achieve improved product performance at each new technology node.  Design for manufacturability (DFM) and design process technology co-optimization (DTCO) are widely used techniques that can ensure the successful delivery of both new processes and products in semiconductor manufacturing.   In this article, we will discuss how 3D (3 dimensional) DTCO can be used to improve product yield and accelerate product delivery dates in semiconductor manufacturing. read more…

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