June 29, 2020

Semiconductor Memory Evolution and Current Challenges

The very first all-electronic memory was the Williams-Kilburn tube, developed in 1947 at Manchester University. It used a cathode ray tube to store bits as dots on the screen’s surface. […]
May 26, 2020
Fig 1: Geometrical CFET evolution from a 2 Nanowires-On- 2 Fins architecture to 2 Nanosheets-On- 2 Nanosheets architecture (NW: Nanowire, NS: Nanosheet, S: Source, D: Drain)

Introducing Nanosheets into Complementary-Field Effect Transistors (CFET)

UNDERSTANDING THE BENEFITS AND CHALLENGES OF A NEW, NEXT-GENERATION SEMICONDUCTOR ARCHITECTURE In our November 2019 blog [1], we discussed using virtual fabrication (SEMulator3D®) to benchmark different process integration options for […]
January 29, 2020
Fig. 1 (a) DRAM Memory Cell, (b) GIDL in Cell Transistor, (c) Dielectric leakage between BLC and SNC, (d) Dielectric leakage at DRAM Capacitor

Identifying DRAM Failures Caused by Leakage Current and Parasitic Capacitance

Leakage current has been a leading cause of device failure in DRAM design, starting with the 20nm technology node. Problems with leakage current in DRAM design can lead to reliability […]
December 16, 2019
Figure 3. Results of etch process applied against base structure (b, middle). The base structure displayed the expected etch results, while the structure with the larger initial opening (c, right) has unexpected topology at the bottom of the structure. The structure with the smaller opening and higher stair shape (a, left) experienced a reduced final etch opening and etch depth (compared to the base structure (b)) at the completion of the modeled etch process.

An Introduction to Semiconductor Process Modeling: Process Specification and Rule Verification

Semiconductor process engineers would love to develop successful process recipes without the guesswork of repeated wafer testing. Unfortunately, developing a successful process can’t be done without some work. This blog […]
July 31, 2019
Top view of slit and channel hole at different nodes

Advanced Patterning Techniques for 3D NAND Devices

Driven by Moore’s law, memory and logic semiconductor manufacturers pursue higher transistor density to improve product cost and performance [1]. In NAND Flash technologies, this has led to the market […]
July 8, 2019
New in SEMulator3D 8.0, powerful new process simulation and analytics capabilities accelerate semiconductor technology development and Design-Technology Co-Optimization (DTCO).

Coventor Adds Process Optimization Features to SEMulator3D 8.0

New Features Enable SEMulator3D 8.0 to Address Both Process Modeling and Device Analysis for Better Insight into Advanced Semiconductor Technology Development
June 25, 2019
Lam Semiconductor Equipment

Controlling Variability using Semiconductor Process Window Optimization

April 18, 2019
Netlist extracted structural components (left) with ports identified in blue. The right figure is the resulting electrical set of components that make up the netlist of R’s and C’s.

Connecting Wafer Level Parasitic Extraction and Netlisting

March 21, 2019
Composite of Virtual SAQP Model with Actual Si Cross-Section Data (animation)

Improving SAQP Patterning Yield using Virtual Fabrication and Advanced Process Control

February 4, 2019
Wedge Cutaway and Schematic – 3D NAND Device

Innovative Solutions to Increase 3D NAND Flash Memory Density

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