December 3, 2021

The Effect of Pattern Loading on BEOL Yield and Reliability during Chemical Mechanical Planarization

CMP (Chemical mechanical planarization) is required during semiconductor processing of many memory and logic devices.  CMP is used to create planar surfaces and achieve uniform layer thickness during semiconductor manufacturing, […]
November 16, 2021
Figure 2.Cutaway of buried wordline spanning saddle-fin transistors.

Understanding Electrical Line Resistance at Advanced Semiconductor Nodes

When evaluating shrinking metal linewidths in advanced semiconductor devices, bulk resistivity is not the sole materials property for deriving electrical resistance. At smaller line dimensions, local resistivity is dominated by […]
October 27, 2021

Using Process Modeling to Enhance Device Uniformity during Self-Aligned Quadruple Patterning

Despite the growing interest in EUV lithography, self-aligned quadruple patterning (SAQP) still holds many technical advantages in pattern consistency, simplicity, and cost.  This is particularly true for very simple and […]
September 14, 2021
Fig. 3: Leakage current distribution from different directions.

Evaluating the Impact of STI Recess Profile Control on Advanced FinFET Device Performance Using Virtual Fabrication

Profile variation is one of the most important problems during semiconductor device manufacturing and scaling.  These variations can degrade both chip yield and device performance.   Virtual fabrication can be used […]
August 19, 2021
Figure 2: A test structure designed to calculate capacitance using 2 nets. The 2 separate nets have 6 ports (P1-P6) and 4 ports (P7-P10), respectively.

Performing High Accuracy Capacitance Analysis using SEMulator3D

Netlist Extraction is an important SEMulator3D® capability that allows a user to extract parasitic resistance and capacitance for different line and via segments during process modeling. This detailed electrical netlist […]
July 20, 2021

Advancing to the 3nm Node and Beyond: Technology, Challenges and Solutions

It seems like yesterday that FinFETs were the answer to device scaling limitations imposed by shrinking gate lengths and required electrostatics. The introduction of FinFETs began at the 22 nm […]
June 16, 2021
Figure 3: On/off-state current distribution at fin bottom (top figures: no residue; bottom figure: with residue).

Using a Virtual DOE to Predict Process Windows and Device Performance of Advanced FinFET Technology

Introduction With continuing FinFET device process scaling, micro loading control becomes increasingly important due to its significant impact on yield and device performance [1-2]. Micro-loading occurs when the local etch […]
May 27, 2021
Figure 2. Simulation results displaying 3 different etch processes followed by 4 different deposition processes

Using Virtual Process Libraries to Improve Semiconductor Manufacturing

People think that semiconductor process simulation libraries should be developed using a perfect theoretical background that is strongly supported by empirical data. This might be true in academic research, where […]
April 15, 2021
Figure 2. SEMulator3D meshes generated for the model shown in Fig. 1. Left: Delaunay; Center: standard; Right: simple. Cross sections are shown for the Delaunay and standard meshes but the full model is shown for the simple mesh because the volume mesh is not accessible and thus no cross-section view is possible.

Connecting SEMulator3D to Third-Party Design and Analysis Software Using Meshing

In the semiconductor modeling world, no simulation software can do everything. That is, each has its own strengths – process modeling, lithography analysis, and circuit design being a few examples. […]
March 8, 2021
Figure 2: Description of the five modules required to build a SSVT-SRAM architecture

Overcoming Design and Process Challenges in Next-Generation SRAM Cell Architectures

Static Random-Access Memory (SRAM) has been a key element for logic circuitry since the early age of the semiconductor industry. The SRAM cell usually consists of six transistors connected to […]
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