January 19, 2021
How can virtual process libraries accelerate semiconductor process development? Process engineers develop ideal solutions to engineering problems using a logical theoretical framework combined with logical engineering steps. Unfortunately, many process […]
December 14, 2020
New integration and patterning schemes used in 3D memory and logic devices have created manufacturing and yield challenges. Industrial focus has shifted from the scaling of predictable unit processes in […]
October 23, 2020
In a DRAM structure, the charging and discharging process of capacitor-based memory cells is directly controlled by the transistor [1].With transistor sizes approaching the lower limits of physical achievability, manufacturing […]
September 23, 2020
In dry etching, the trajectory of accelerated ions is non-uniform and non-vertical, due to collisions with gas molecules and other random thermal effects (Figure 1). This has an impact on […]
August 24, 2020
Understanding Advanced Packaging Technologies and Their Impact on the Next Generation of Electronics
Chip packaging has expanded from its conventional definition of providing protection and I/O for a discrete chip, to encompassing a growing number of schemes for interconnecting multiple types of chips. […]
July 21, 2020
Process engineers and integrators can use virtual process modeling to test alternative process schemes and architectures without relying on wafer-based testing. One important aspect of building an accurate process model […]
June 29, 2020
The very first all-electronic memory was the Williams-Kilburn tube, developed in 1947 at Manchester University. It used a cathode ray tube to store bits as dots on the screen’s surface. […]
May 26, 2020
UNDERSTANDING THE BENEFITS AND CHALLENGES OF A NEW, NEXT-GENERATION SEMICONDUCTOR ARCHITECTURE In our November 2019 blog [1], we discussed using virtual fabrication (SEMulator3D®) to benchmark different process integration options for […]
January 29, 2020
Leakage current has been a leading cause of device failure in DRAM design, starting with the 20nm technology node. Problems with leakage current in DRAM design can lead to reliability […]
December 16, 2019
Semiconductor process engineers would love to develop successful process recipes without the guesswork of repeated wafer testing. Unfortunately, developing a successful process can’t be done without some work. This blog […]