January 29, 2020
Fig. 1 (a) DRAM Memory Cell, (b) GIDL in Cell Transistor, (c) Dielectric leakage between BLC and SNC, (d) Dielectric leakage at DRAM Capacitor
Published by Tae Yeon Oh at January 29, 2020
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Identifying DRAM Failures Caused by Leakage Current and Parasitic Capacitance

Leakage current has been a leading cause of device failure in DRAM design, starting with the 20nm technology node. Problems with leakage current in DRAM design can lead to reliability […]
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December 16, 2019
Figure 3. Results of etch process applied against base structure (b, middle). The base structure displayed the expected etch results, while the structure with the larger initial opening (c, right) has unexpected topology at the bottom of the structure. The structure with the smaller opening and higher stair shape (a, left) experienced a reduced final etch opening and etch depth (compared to the base structure (b)) at the completion of the modeled etch process.
Published by Jeonghoon Kim at December 16, 2019
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An Introduction to Semiconductor Process Modeling: Process Specification and Rule Verification

Semiconductor process engineers would love to develop successful process recipes without the guesswork of repeated wafer testing. Unfortunately, developing a successful process can’t be done without some work. This blog […]
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July 31, 2019
Top view of slit and channel hole at different nodes
Published by Yu De Chen at July 31, 2019
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Advanced Patterning Techniques for 3D NAND Devices

Driven by Moore’s law, memory and logic semiconductor manufacturers pursue higher transistor density to improve product cost and performance [1]. In NAND Flash technologies, this has led to the market […]
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July 8, 2019
New in SEMulator3D 8.0, powerful new process simulation and analytics capabilities accelerate semiconductor technology development and Design-Technology Co-Optimization (DTCO).
Published by Coventor at July 8, 2019
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Coventor Adds Process Optimization Features to SEMulator3D 8.0

New Features Enable SEMulator3D 8.0 to Address Both Process Modeling and Device Analysis for Better Insight into Advanced Semiconductor Technology Development
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June 25, 2019
Lam Semiconductor Equipment
Published by Benjamin Vincent at June 25, 2019
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Controlling Variability using Semiconductor Process Window Optimization

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April 18, 2019
Netlist extracted structural components (left) with ports identified in blue. The right figure is the resulting electrical set of components that make up the netlist of R’s and C’s.
Published by Michael Hargrove at April 18, 2019
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Connecting Wafer Level Parasitic Extraction and Netlisting

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March 21, 2019
Composite of Virtual SAQP Model with Actual Si Cross-Section Data (animation)
Published by Benjamin Vincent at March 21, 2019
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Improving SAQP Patterning Yield using Virtual Fabrication and Advanced Process Control

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February 4, 2019
Wedge Cutaway and Schematic – 3D NAND Device
Published by Timothy Yang at February 4, 2019
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Innovative Solutions to Increase 3D NAND Flash Memory Density

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January 15, 2019
Y-branch structure (SiO2 upper and lower claddings not shown)
Published by Ryan Miller at January 15, 2019
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Analyzing Worst-Case Silicon Photonic Device Performance Through Process Modeling and Optical Simulation

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August 16, 2018
Coventor-August-2018-Blog-Figure-2-Resulting third party software modeling of Y-splitter optical properties.
Published by Michael Hargrove at August 16, 2018
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A Review of Silicon Photonics: Using Process Simulation to Design Silicon Photonics Devices

With the end of Moore’s Law rapidly approaching, or as some folks say – “already here”, new applications of older technologies are gaining attention. One specific area of interest is […]
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