March 8, 2021
Figure 2: Description of the five modules required to build a SSVT-SRAM architecture

Overcoming Design and Process Challenges in Next-Generation SRAM Cell Architectures

Static Random-Access Memory (SRAM) has been a key element for logic circuitry since the early age of the semiconductor industry. The SRAM cell usually consists of six transistors connected to […]
February 22, 2021
Fig. 1. Key process steps comparison of the three structures.

The future of FinFETs at 5nm and beyond: Using combined process and circuit modeling to estimate the performance of the next generation of semiconductors

While contact gate pitch (GP) and fin pitch (FP) scaling continues to provide higher performance and lower power to FinFET platforms, controlling RC parasitics and achieving higher transistor performance at […]
January 19, 2021
Figure 4. Simulation result of a specific etch process library on three different structures

An Introduction to Virtual Semiconductor Process Evaluation

How can virtual process libraries accelerate semiconductor process development? Process engineers develop ideal solutions to engineering problems using a logical theoretical framework combined with logical engineering steps.  Unfortunately, many process […]
December 14, 2020
  Figure 2:  SEMulator3D identifies device electrodes in a 3D structure and simulates device characteristics similar to TCAD software, but without the need for time-consuming TCAD modeling.

Process Window Optimization of DRAM by Virtual Fabrication

New integration and patterning schemes used in 3D memory and logic devices have created manufacturing and yield challenges.  Industrial focus has shifted from the scaling of predictable unit processes in […]
October 23, 2020
Fig. 6: Channel leakage profile from the fin surface to the fin center at different sidewall angle splits.

Micro Loading and its Impact on Device Performance: A Wiggling Active Area Case in an Advanced DRAM Process

In a DRAM structure, the charging and discharging process of capacitor-based memory cells is directly controlled by the transistor [1].With transistor sizes approaching the lower limits of physical achievability, manufacturing […]
September 23, 2020
Fig 5: ALD thickness dependence and layer etch. Using profiled anisotropic etching of the SiO2 (blue) and SiN (green), the resulting hole shape can be determined using varying ALD thicknesses. The best shape is found at a 23.5 nm ALD value, using a Semulator 3D visibility etch model that was previously validated again actual etch results.

Accelerating the Development of Dry Etch Processes during Feature Dependent Etch

In dry etching, the trajectory of accelerated ions is non-uniform and non-vertical, due to collisions with gas molecules and other random thermal effects (Figure 1). This has an impact on […]
August 24, 2020
Figure 2: Example of a device package.

Understanding Advanced Packaging Technologies and Their Impact on the Next Generation of Electronics

Chip packaging has expanded from its conventional definition of providing protection and I/O for a discrete chip, to encompassing a growing number of schemes for interconnecting multiple types of chips. […]
July 21, 2020
Figure 4: SEMulator3D model of the Spacer 1 Oxide Fin CD after PMC.   The oxide spacer is turquoise, and the red etch stop layer is amorphous silicon. TEM image with the SEMulator3D image aligned to show visual comparison. Note that sidewall angle and line to line measurements can be used with Process Model Calibration to tune for the deformation caused by the mandrel removal.  

Process Model Calibration: The Key to Building Predictive and Accurate 3D Process Models

Process engineers and integrators can use virtual process modeling to test alternative process schemes and architectures without relying on wafer-based testing. One important aspect of building an accurate process model […]
June 29, 2020

Semiconductor Memory Evolution and Current Challenges

The very first all-electronic memory was the Williams-Kilburn tube, developed in 1947 at Manchester University. It used a cathode ray tube to store bits as dots on the screen’s surface. […]
May 26, 2020
Fig 1: Geometrical CFET evolution from a 2 Nanowires-On- 2 Fins architecture to 2 Nanosheets-On- 2 Nanosheets architecture (NW: Nanowire, NS: Nanosheet, S: Source, D: Drain)

Introducing Nanosheets into Complementary-Field Effect Transistors (CFET)

UNDERSTANDING THE BENEFITS AND CHALLENGES OF A NEW, NEXT-GENERATION SEMICONDUCTOR ARCHITECTURE In our November 2019 blog [1], we discussed using virtual fabrication (SEMulator3D®) to benchmark different process integration options for […]
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