May 30, 2023
Figure 1 displays a single cell of a conventional DRAM that consists of 2 Word Lines (WLs), a Bit Line (BL) and 2 Storage Node Contacts (SNC) in Figure 1(a). There are 3 images in the figure. The Saddle Fin is produced during the WL etch step (prior to WL metal deposition) and is located below the cell wordline (Figure 1(b), right center inside a yellow dotted circle). The Saddle Fin structure can be seen in detail by making a vertical cut in the wordline direction (Fig.1(b), right). During device simulation, the Saddle Fin performance can be measured by virtually cropping a transistor and adding ports at the Gate, Source and Drain after an SNC Process (Fig.1(c), showing the gate, source and drain).
Published by Tae Yeon Oh at May 30, 2023
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Improving DRAM Device Performance Through Saddle Fin Process Optimization

As DRAM technology nodes have scaled down, access transistor issues have been highlighted due to weak gate controllability. Saddle Fins with Buried Channel Array Transistors (BCAT) have subsequently been introduced […]
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April 13, 2023
Figure 6 (left to right): Different profiles using pattern dependence for the antenna and sharp head shapes. a) Antenna shape with POR flow (b) Antenna profile with a gate CD of 26nm (c) Sharp head profile with a gate CD of 28nm (d) Sharp head profile with an etch.
Published by Pradeep Nanja at April 13, 2023
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The Impact of Metal Gate Recess Profile on Transistor Resistance and Capacitance

Introduction In logic devices such as FinFETs (field-effect transistors), metal gate parasitic capacitance can negatively impact electrical performance. One way to reduce this parasitic capacitance is to optimize the metal […]
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March 22, 2023
Figure 1a (left) displays the process of performing Physical Vapor Deposition (PVD), including Cu bombardment and filling of voids. Figure 1b (right) displays the process of performing Ion Beam Etch (IBE), including ion beam bombardment, mask shadowing and etch regions.
Published by Timothy Yang at March 22, 2023
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A Deposition and Etch Technique to Lower Resistance of Semiconductor Metal Lines

Introduction Cu’s resistivity depends on its crystal structure, void volume, grain boundaries and material interface mismatch, which becomes more significant at smaller scales.  The formation of Cu wires is traditionally […]
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January 13, 2023
Figure 4 displays a single image showing how surface roughness can get transferred to materials etched or deposited later. In this image, the surface roughness has led to scumming, which in turn caused lines to get shorted. The figure shows uneven lines due to surface roughness, with material left behind that crosses two of the lines and creates a short.
Published by Sumant Sarkar at January 13, 2023
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Modeling of Line and Surface Roughness in Semiconductor Processing

Line edge roughness (LER) can occur during the exposure step in lithography [1-2]. Similarly, etch and deposition process steps can leave a roughness on semiconductor surfaces. LER is a stochastic […]
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December 19, 2022
Figure 2. Backside power delivery using buried power rails, based on [2] (not to scale).
Published by Sandy Wen at December 19, 2022
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The Other Side of the Wafer: The Latest Developments in Backside Power Delivery

At the beginning of my career in semiconductor equipment, the backside of the wafer was a source of anxiety. In one memorable instance in my early career, several wafers flew […]
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November 8, 2022
Fig 4a-c: Process model flow of film thickness at the isolated region of  a) 20 nm, b) 10 nm and c) 0 nm with corresponding trench etch depth from bottom of resist.
Published by Pradeep Nanja at November 8, 2022
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In situ Metrology for Etch Endpoint Detection

Introduction The semiconductor industry has been focused on scaling and developing advanced technologies using advanced etch tools and techniques. With decreasing semiconductor device dimensions and increases in process complexity, the […]
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October 27, 2022
Figure 1 - SEMulator3D® process flow for creating an airgap in a FinFET model. The visibility deposit step creates the airgap by pinching off the airgap at the top. The CMP step is then used to remove the excess nitride. Scale bar is 10nm. The airgap reduces the parasitic capacitance between gate and source/drain. The size of the airgap can be controlled by varying the etch depth, tilt and source sigma of the etching reagents.
Published by Sumant Sarkar at October 27, 2022
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Creating Airgaps to Reduce Parasitic Capacitance in FEOL

Reducing the parasitic capacitance between the gate metal and the source/drain contact of a transistor can decrease device switching delays. One way to reduce parasitic capacitance is to reduce the […]
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September 22, 2022
Figure 2. Virtual metrology results for minimum and maximum area.
Published by QingPeng Wang at September 22, 2022
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Pathfinding by process window modeling: Advanced DRAM capacitor patterning process window evaluation using virtual fabrication

With continuous device scaling, process windows have become narrower and narrower due to smaller feature sizes and greater process step variability [1]. A key task during the R&D stage of […]
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August 18, 2022
Figure 2: (a) Layout design, (b) Top view of a typical metal line generated, (c) cross sectional view of the metal line, (d) LER status of RMS and Correlation length split.
Published by Yu De Chen at August 18, 2022
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How does Line Edge Roughness (LER) affect Semiconductor Performance at Advanced Nodes ?

Introduction BEOL metal line RC delay has become a dominant factor that limits chip performance at advanced nodes [1]. Smaller metal line pitches require a narrower line CD and line-to-line […]
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July 15, 2022
Figure 4:   Current Density Top-Down View of Virtual-Model Experiment Runs. Each experimental setup (shown in Images A, B and C) have different experimental run treatments (refer to Figure 1 for treatment descriptions). Image A: The rail is not continuous, causing the current to flow through the interior of the wordline. Image B: The memory hole size is the same as in Image A, but the wide rail allows current to flow along the outer edges of the wordline. Image C:  A nominal memory cell hole size is shown.  In this case, the nominal wordline rail distance supports a more uniform current density pattern.
Published by Brett Lowe at July 15, 2022
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3D NAND Virtual Process Troubleshooting and Investigation with SEMulator3D

Modern semiconductor processes are extremely complicated and involve thousands of interacting individual process steps. During the development of these process steps, roadblocks and barriers are often encountered in the form […]
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