May 30, 2023

Improving DRAM Device Performance Through Saddle Fin Process Optimization

As DRAM technology nodes have scaled down, access transistor issues have been highlighted due to weak gate controllability. Saddle Fins with Buried Channel Array Transistors (BCAT) have subsequently been introduced […]
April 13, 2023

The Impact of Metal Gate Recess Profile on Transistor Resistance and Capacitance

Introduction In logic devices such as FinFETs (field-effect transistors), metal gate parasitic capacitance can negatively impact electrical performance. One way to reduce this parasitic capacitance is to optimize the metal […]
March 22, 2023

A Deposition and Etch Technique to Lower Resistance of Semiconductor Metal Lines

Introduction Cu’s resistivity depends on its crystal structure, void volume, grain boundaries and material interface mismatch, which becomes more significant at smaller scales.  The formation of Cu wires is traditionally […]
January 13, 2023

Modeling of Line and Surface Roughness in Semiconductor Processing

Line edge roughness (LER) can occur during the exposure step in lithography [1-2]. Similarly, etch and deposition process steps can leave a roughness on semiconductor surfaces. LER is a stochastic […]
December 19, 2022

The Other Side of the Wafer: The Latest Developments in Backside Power Delivery

At the beginning of my career in semiconductor equipment, the backside of the wafer was a source of anxiety. In one memorable instance in my early career, several wafers flew […]
November 8, 2022

In situ Metrology for Etch Endpoint Detection

Introduction The semiconductor industry has been focused on scaling and developing advanced technologies using advanced etch tools and techniques. With decreasing semiconductor device dimensions and increases in process complexity, the […]
October 27, 2022

Creating Airgaps to Reduce Parasitic Capacitance in FEOL

Reducing the parasitic capacitance between the gate metal and the source/drain contact of a transistor can decrease device switching delays. One way to reduce parasitic capacitance is to reduce the […]
September 22, 2022

Pathfinding by process window modeling: Advanced DRAM capacitor patterning process window evaluation using virtual fabrication

With continuous device scaling, process windows have become narrower and narrower due to smaller feature sizes and greater process step variability [1]. A key task during the R&D stage of […]
August 18, 2022

How does Line Edge Roughness (LER) affect Semiconductor Performance at Advanced Nodes ?

Introduction BEOL metal line RC delay has become a dominant factor that limits chip performance at advanced nodes [1]. Smaller metal line pitches require a narrower line CD and line-to-line […]
July 15, 2022

3D NAND Virtual Process Troubleshooting and Investigation with SEMulator3D

Modern semiconductor processes are extremely complicated and involve thousands of interacting individual process steps. During the development of these process steps, roadblocks and barriers are often encountered in the form […]