September 22, 2022
Figure 2. Virtual metrology results for minimum and maximum area.

Pathfinding by process window modeling: Advanced DRAM capacitor patterning process window evaluation using virtual fabrication

With continuous device scaling, process windows have become narrower and narrower due to smaller feature sizes and greater process step variability [1]. A key task during the R&D stage of […]
August 18, 2022
Figure 2: (a) Layout design, (b) Top view of a typical metal line generated, (c) cross sectional view of the metal line, (d) LER status of RMS and Correlation length split.

How does Line Edge Roughness (LER) affect Semiconductor Performance at Advanced Nodes ?

Introduction BEOL metal line RC delay has become a dominant factor that limits chip performance at advanced nodes [1]. Smaller metal line pitches require a narrower line CD and line-to-line […]
July 15, 2022
Figure 4:   Current Density Top-Down View of Virtual-Model Experiment Runs. Each experimental setup (shown in Images A, B and C) have different experimental run treatments (refer to Figure 1 for treatment descriptions). Image A: The rail is not continuous, causing the current to flow through the interior of the wordline. Image B: The memory hole size is the same as in Image A, but the wide rail allows current to flow along the outer edges of the wordline. Image C:  A nominal memory cell hole size is shown.  In this case, the nominal wordline rail distance supports a more uniform current density pattern.

3D NAND Virtual Process Troubleshooting and Investigation with SEMulator3D

Modern semiconductor processes are extremely complicated and involve thousands of interacting individual process steps. During the development of these process steps, roadblocks and barriers are often encountered in the form […]
April 15, 2022
Figure 1:  Two different metal line connection designs under consideration

Accelerating Semiconductor Module Development using Shared Process Libraries

One of the fastest ways to predict semiconductor manufacturing final results is by adding together the results of performing individual process steps. Unfortunately, this prediction might ignore critical defects that […]
March 14, 2022
Figure 2: A semi-damascene process flow for BEOL device integration using the new mask set

BEOL integration for the 1.5nm node and beyond

Introduction As we approach the 1.5nm node and beyond, new BEOL device integration challenges will be presented.  These challenges include the need for smaller metal pitches, along with support for […]
February 11, 2022
Figure 3: DEDED Contour, Level Plot and Output Structure of DOE2

Accelerating Semiconductor Process Development Using Virtual Design of Experiments

Design of Experiments (DOE) is a powerful concept in semiconductor engineering research and development.   DOEs are sets of experiments used to explore the sensitivity of experimental variables and their effect […]
January 4, 2022

A Fantastic Voyage into Semiconductor Devices

When I was a small child, I remember watching a 1966 American sci-fi adventure movie called “Fantastic Voyage”  (the Korean title was “Micro Squad”) on an old black-and-white TV. The […]
December 3, 2021

The Effect of Pattern Loading on BEOL Yield and Reliability during Chemical Mechanical Planarization

CMP (Chemical mechanical planarization) is required during semiconductor processing of many memory and logic devices.  CMP is used to create planar surfaces and achieve uniform layer thickness during semiconductor manufacturing, […]
November 16, 2021
Figure 2.Cutaway of buried wordline spanning saddle-fin transistors.

Understanding Electrical Line Resistance at Advanced Semiconductor Nodes

When evaluating shrinking metal linewidths in advanced semiconductor devices, bulk resistivity is not the sole materials property for deriving electrical resistance. At smaller line dimensions, local resistivity is dominated by […]
October 27, 2021

Using Process Modeling to Enhance Device Uniformity during Self-Aligned Quadruple Patterning

Despite the growing interest in EUV lithography, self-aligned quadruple patterning (SAQP) still holds many technical advantages in pattern consistency, simplicity, and cost.  This is particularly true for very simple and […]
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