June 16, 2021
Figure 3: On/off-state current distribution at fin bottom (top figures: no residue; bottom figure: with residue).

Using a Virtual DOE to Predict Process Windows and Device Performance of Advanced FinFET Technology

Introduction With continuing FinFET device process scaling, micro loading control becomes increasingly important due to its significant impact on yield and device performance [1-2]. Micro-loading occurs when the local etch […]
May 27, 2021
Figure 2. Simulation results displaying 3 different etch processes followed by 4 different deposition processes

Using Virtual Process Libraries to Improve Semiconductor Manufacturing

People think that semiconductor process simulation libraries should be developed using a perfect theoretical background that is strongly supported by empirical data. This might be true in academic research, where […]
April 15, 2021
Figure 2. SEMulator3D meshes generated for the model shown in Fig. 1. Left: Delaunay; Center: standard; Right: simple. Cross sections are shown for the Delaunay and standard meshes but the full model is shown for the simple mesh because the volume mesh is not accessible and thus no cross-section view is possible.

Connecting SEMulator3D to Third-Party Design and Analysis Software Using Meshing

In the semiconductor modeling world, no simulation software can do everything. That is, each has its own strengths – process modeling, lithography analysis, and circuit design being a few examples. […]
March 8, 2021
Figure 2: Description of the five modules required to build a SSVT-SRAM architecture

Overcoming Design and Process Challenges in Next-Generation SRAM Cell Architectures

Static Random-Access Memory (SRAM) has been a key element for logic circuitry since the early age of the semiconductor industry. The SRAM cell usually consists of six transistors connected to […]
February 22, 2021
Fig. 1. Key process steps comparison of the three structures.

The future of FinFETs at 5nm and beyond: Using combined process and circuit modeling to estimate the performance of the next generation of semiconductors

While contact gate pitch (GP) and fin pitch (FP) scaling continues to provide higher performance and lower power to FinFET platforms, controlling RC parasitics and achieving higher transistor performance at […]
January 19, 2021
Figure 4. Simulation result of a specific etch process library on three different structures

An Introduction to Virtual Semiconductor Process Evaluation

How can virtual process libraries accelerate semiconductor process development? Process engineers develop ideal solutions to engineering problems using a logical theoretical framework combined with logical engineering steps.  Unfortunately, many process […]
December 14, 2020
  Figure 2:  SEMulator3D identifies device electrodes in a 3D structure and simulates device characteristics similar to TCAD software, but without the need for time-consuming TCAD modeling.

Process Window Optimization of DRAM by Virtual Fabrication

New integration and patterning schemes used in 3D memory and logic devices have created manufacturing and yield challenges.  Industrial focus has shifted from the scaling of predictable unit processes in […]
October 23, 2020
Fig. 6: Channel leakage profile from the fin surface to the fin center at different sidewall angle splits.

Micro Loading and its Impact on Device Performance: A Wiggling Active Area Case in an Advanced DRAM Process

In a DRAM structure, the charging and discharging process of capacitor-based memory cells is directly controlled by the transistor [1].With transistor sizes approaching the lower limits of physical achievability, manufacturing […]
September 23, 2020
Fig 5: ALD thickness dependence and layer etch. Using profiled anisotropic etching of the SiO2 (blue) and SiN (green), the resulting hole shape can be determined using varying ALD thicknesses. The best shape is found at a 23.5 nm ALD value, using a Semulator 3D visibility etch model that was previously validated again actual etch results.

Accelerating the Development of Dry Etch Processes during Feature Dependent Etch

In dry etching, the trajectory of accelerated ions is non-uniform and non-vertical, due to collisions with gas molecules and other random thermal effects (Figure 1). This has an impact on […]
August 24, 2020
Figure 2: Example of a device package.

Understanding Advanced Packaging Technologies and Their Impact on the Next Generation of Electronics

Chip packaging has expanded from its conventional definition of providing protection and I/O for a discrete chip, to encompassing a growing number of schemes for interconnecting multiple types of chips. […]
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