April 15, 2022
Figure 1:  Two different metal line connection designs under consideration

Accelerating Semiconductor Module Development using Shared Process Libraries

One of the fastest ways to predict semiconductor manufacturing final results is by adding together the results of performing individual process steps. Unfortunately, this prediction might ignore critical defects that […]
March 14, 2022
Figure 2: A semi-damascene process flow for BEOL device integration using the new mask set

BEOL integration for the 1.5nm node and beyond

Introduction As we approach the 1.5nm node and beyond, new BEOL device integration challenges will be presented.  These challenges include the need for smaller metal pitches, along with support for […]
February 11, 2022
Figure 3: DEDED Contour, Level Plot and Output Structure of DOE2

Accelerating Semiconductor Process Development Using Virtual Design of Experiments

Design of Experiments (DOE) is a powerful concept in semiconductor engineering research and development.   DOEs are sets of experiments used to explore the sensitivity of experimental variables and their effect […]
January 4, 2022

A Fantastic Voyage into Semiconductor Devices

When I was a small child, I remember watching a 1966 American sci-fi adventure movie called “Fantastic Voyage”  (the Korean title was “Micro Squad”) on an old black-and-white TV. The […]
December 3, 2021

The Effect of Pattern Loading on BEOL Yield and Reliability during Chemical Mechanical Planarization

CMP (Chemical mechanical planarization) is required during semiconductor processing of many memory and logic devices.  CMP is used to create planar surfaces and achieve uniform layer thickness during semiconductor manufacturing, […]
November 16, 2021
Figure 2.Cutaway of buried wordline spanning saddle-fin transistors.

Understanding Electrical Line Resistance at Advanced Semiconductor Nodes

When evaluating shrinking metal linewidths in advanced semiconductor devices, bulk resistivity is not the sole materials property for deriving electrical resistance. At smaller line dimensions, local resistivity is dominated by […]
October 27, 2021

Using Process Modeling to Enhance Device Uniformity during Self-Aligned Quadruple Patterning

Despite the growing interest in EUV lithography, self-aligned quadruple patterning (SAQP) still holds many technical advantages in pattern consistency, simplicity, and cost.  This is particularly true for very simple and […]
September 14, 2021
Fig. 3: Leakage current distribution from different directions.

Evaluating the Impact of STI Recess Profile Control on Advanced FinFET Device Performance Using Virtual Fabrication

Profile variation is one of the most important problems during semiconductor device manufacturing and scaling.  These variations can degrade both chip yield and device performance.   Virtual fabrication can be used […]
August 19, 2021
Figure 2: A test structure designed to calculate capacitance using 2 nets. The 2 separate nets have 6 ports (P1-P6) and 4 ports (P7-P10), respectively.

Performing High Accuracy Capacitance Analysis using SEMulator3D

Netlist Extraction is an important SEMulator3D® capability that allows a user to extract parasitic resistance and capacitance for different line and via segments during process modeling. This detailed electrical netlist […]
July 20, 2021

Advancing to the 3nm Node and Beyond: Technology, Challenges and Solutions

It seems like yesterday that FinFETs were the answer to device scaling limitations imposed by shrinking gate lengths and required electrostatics. The introduction of FinFETs began at the 22 nm […]
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