January 13, 2023
Line edge roughness (LER) can occur during the exposure step in lithography [1-2]. Similarly, etch and deposition process steps can leave a roughness on semiconductor surfaces. LER is a stochastic […]
December 19, 2022
![Figure 2. Backside power delivery using buried power rails, based on [2] (not to scale).](https://www.coventor.com/wp-content/uploads/2022/12/Figure-2-December-2022-Coventor-website-blog-from-Sandy-Wen-960x720.png)
At the beginning of my career in semiconductor equipment, the backside of the wafer was a source of anxiety. In one memorable instance in my early career, several wafers flew […]
November 8, 2022
Introduction The semiconductor industry has been focused on scaling and developing advanced technologies using advanced etch tools and techniques. With decreasing semiconductor device dimensions and increases in process complexity, the […]
October 27, 2022
Reducing the parasitic capacitance between the gate metal and the source/drain contact of a transistor can decrease device switching delays. One way to reduce parasitic capacitance is to reduce the […]
September 22, 2022
With continuous device scaling, process windows have become narrower and narrower due to smaller feature sizes and greater process step variability [1]. A key task during the R&D stage of […]
August 18, 2022
Introduction BEOL metal line RC delay has become a dominant factor that limits chip performance at advanced nodes [1]. Smaller metal line pitches require a narrower line CD and line-to-line […]
July 15, 2022
Modern semiconductor processes are extremely complicated and involve thousands of interacting individual process steps. During the development of these process steps, roadblocks and barriers are often encountered in the form […]
April 15, 2022
One of the fastest ways to predict semiconductor manufacturing final results is by adding together the results of performing individual process steps. Unfortunately, this prediction might ignore critical defects that […]
March 14, 2022
Introduction As we approach the 1.5nm node and beyond, new BEOL device integration challenges will be presented. These challenges include the need for smaller metal pitches, along with support for […]
February 11, 2022
Design of Experiments (DOE) is a powerful concept in semiconductor engineering research and development. DOEs are sets of experiments used to explore the sensitivity of experimental variables and their effect […]