June 22, 2018
Coventor_June_2018_blog-fig1.a CFET Cross section showing a continuous nitride layer isolating the two M0 levels

Practical Methods to Overcome the Challenges of 3D Logic Design

What should you do If you don’t have enough room on your floor to store all your old boxes? Luckily, we live in a 3D world, and you can start […]
April 17, 2018
Basic process flow and structure build of a 16 nm RAM cell (left), cropped nFET pull-down device and resulting DUT (right).

Transistor-Level Performance Evaluation Based on Wafer-Level Process Modeling

Three years ago, I wrote a blog entitled “Linking Virtual Wafer Fabrication Modeling with Device-level TCAD Simulation” in which I described the seamless connection between the SEMulator3D® virtual wafer fabrication […]
April 13, 2018
Example of metal connections in Back End of Line (BEOL) development, and highlighted hotspots.

Advanced 3D Design Technology Co-Optimization for Manufacturability

Yield and cost have always been critical factors for both manufacturers and designers of semiconductor products. It is a continuous challenge to meet targets of both yield and cost, due […]
March 21, 2018

Improving Patterning Yield at the 5 nm Semiconductor Node

Engineering decisions are always data-driven.  As scientists, we only believe in facts and not in intuition or feelings. At the manufacturing stage, the semiconductor industry is eager to provide data […]
February 28, 2018
New in SEMulator3D 7.0: Powerful new process and device simulation capabilities

Coventor Adds Device Analysis Capabilities to SEMulator3D 7.0

New Features Enable SEMulator3D Version 7.0 to Address Both Process Modeling and Device Analysis for Better Insight into Advanced Semiconductor Technology Development CARY, NC– February 28, 2018 – February 26, […]
November 17, 2017

SEMulator3D Honored as UBM ACE Award Finalist

Coventor’s Virtual Fabrication Platform Recognized for Significantly Improving Electronics Manufacturing CARY, NC– November 17, 2017 – Coventor®, Inc. a Lam Research Company and leading supplier of virtual fabrication solutions for […]
October 18, 2017
SEMulator3D created air gap process flows based on published reports.

Reducing BEOL Parasitic Capacitance using Air Gaps

Reducing back-end-of-line (BEOL) interconnect parasitic capacitance remains a focus for advanced technology node development. Porous low-k dielectric materials have been used to achieve reduced capacitance, however, these materials remain fragile […]
September 19, 2017
FinFET Process Step Illustration

Using Advanced Statistical Analysis to improve FinFET transistor performance

Trial and error wafer fabrication is commonly used to study the effect of process changes in the development of FinFET and other advanced semiconductor technologies. Due to the interaction of upstream […]
June 26, 2017
New-in-SEMulator3D-6.1

Coventor Announces SEMulator3D 6.1 and New Analytics Capabilities

Coventor’s Virtual Fabrication Platform Provides Statistical Insight into Process Variation Challenges CARY, NC– June 22, 2016 – Coventor®, Inc., the leading supplier of automated software solutions for semiconductor devices and […]
May 17, 2017

What drives SADP BEOL variability?

Until EUV lithography becomes a reality, multiple patterning technologies such as triple litho-etch (LELELE), self-aligned double patterning (SADP), and self-aligned quadruple patterning (SAQP) are being used to meet the stringent […]
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