April 15, 2020
Co-simulation of the package and transducer

Cutting-Edge MEMS Process, Device and Simulation Technologies: IEEE MEMS 2020 Conference Review

The IEEE MEMS conference was held in Vancouver during January 2020. We attended the conference to meet with our customers and to see what new developments are being made in […]
December 16, 2019
Figure 3. Results of etch process applied against base structure (b, middle). The base structure displayed the expected etch results, while the structure with the larger initial opening (c, right) has unexpected topology at the bottom of the structure. The structure with the smaller opening and higher stair shape (a, left) experienced a reduced final etch opening and etch depth (compared to the base structure (b)) at the completion of the modeled etch process.

An Introduction to Semiconductor Process Modeling: Process Specification and Rule Verification

Semiconductor process engineers would love to develop successful process recipes without the guesswork of repeated wafer testing. Unfortunately, developing a successful process can’t be done without some work. This blog […]
July 31, 2019
Top view of slit and channel hole at different nodes

Advanced Patterning Techniques for 3D NAND Devices

Driven by Moore’s law, memory and logic semiconductor manufacturers pursue higher transistor density to improve product cost and performance [1]. In NAND Flash technologies, this has led to the market […]
May 21, 2019

Challenges and Solutions for Silicon Wafer Bevel Defects during 3D NAND Flash Manufacturing

February 4, 2019
Wedge Cutaway and Schematic – 3D NAND Device

Innovative Solutions to Increase 3D NAND Flash Memory Density

October 12, 2018
3D NAND Memory Array and Key Process Challenges (Source: Lam Research)

3D NAND: Challenges beyond 96-Layer Memory Arrays

July 20, 2018
Coventor-July_2018_blog-Figure5_FDSOI_SG_paper

Everything You Need to Know about FDSOI Technology – Advantages, Disadvantages, and Applications of FDSOI

This blog is a summary of a technical and business review of FDSOI technology. Read the full paper here. Over the past decades, transistor feature size has continuously decreased, leading […]
January 17, 2018
Basic cross-section of an FD-SOI transistor. (Source: STMicroelectronics)

Future Outlook: The Advantages of Fully Depleted Silicon on Insulator (FD-SOI) Technology

If my memory serves me well, it was at the 1989 Device Research Conference where the potential merits of SOI (Silicon on Insulator) technology were discussed in a heated evening […]
December 19, 2017
2017 IEDM Panel Speakers on Stage

What the Experts Think: Delivering the Next 5 Years of Semiconductor Technology

Coventor recently sponsored an expert panel discussion at IEDM 2017 to discuss how we might advance the semiconductor industry into the next generation of technology.  The panel discussed alternative methods […]
November 20, 2017
Delivering-the-Next-5-Years-of-Semiconductor-Technology

Delivering the Next 5 Years of Semiconductor Technology

New, advanced semiconductor processing and architectural technologies take years to perfect and put into production. In the meantime, semiconductor customers continue to demand faster, smaller and higher functioning devices. Semiconductor […]
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