December 14, 2021

Digital Twins for MEMS Product Development

A digital twin is a digital representation of a real-world item, and includes software objects or models that represents these real-world items.   In MEMS product development, digital twins (or software […]
November 16, 2020
Lam_GAA_10.26.20_sq

FinFETs Give Way to Gate-All-Around

When they were first commercialized at the 22 nm node, finFETs represented a revolutionary change to the way we build transistors, the tiny switches in the “brains” of a chip. As […]
August 24, 2020
Figure 2: Example of a device package.

Understanding Advanced Packaging Technologies and Their Impact on the Next Generation of Electronics

Chip packaging has expanded from its conventional definition of providing protection and I/O for a discrete chip, to encompassing a growing number of schemes for interconnecting multiple types of chips. […]
June 29, 2020

Semiconductor Memory Evolution and Current Challenges

The very first all-electronic memory was the Williams-Kilburn tube, developed in 1947 at Manchester University. It used a cathode ray tube to store bits as dots on the screen’s surface. […]
June 26, 2020
Virtually every MEMS and sensor device inside the latest electronic products has been made using Lam Research equipment

Enabling Better MEMS from Concept to High Volume Manufacturing

Lam Research® is one of the top equipment suppliers in the semiconductor ecosystem. As a trusted, collaborative partner to the world’s leading semiconductor companies, Lam Research is a fundamental enabler […]
April 15, 2020
Co-simulation of the package and transducer

Cutting-Edge MEMS Process, Device and Simulation Technologies: IEEE MEMS 2020 Conference Review

The IEEE MEMS conference was held in Vancouver during January 2020. We attended the conference to meet with our customers and to see what new developments are being made in […]
December 16, 2019
Figure 3. Results of etch process applied against base structure (b, middle). The base structure displayed the expected etch results, while the structure with the larger initial opening (c, right) has unexpected topology at the bottom of the structure. The structure with the smaller opening and higher stair shape (a, left) experienced a reduced final etch opening and etch depth (compared to the base structure (b)) at the completion of the modeled etch process.

An Introduction to Semiconductor Process Modeling: Process Specification and Rule Verification

Semiconductor process engineers would love to develop successful process recipes without the guesswork of repeated wafer testing. Unfortunately, developing a successful process can’t be done without some work. This blog […]
July 31, 2019
Top view of slit and channel hole at different nodes

Advanced Patterning Techniques for 3D NAND Devices

Driven by Moore’s law, memory and logic semiconductor manufacturers pursue higher transistor density to improve product cost and performance [1]. In NAND Flash technologies, this has led to the market […]
May 21, 2019

Challenges and Solutions for Silicon Wafer Bevel Defects during 3D NAND Flash Manufacturing

As semiconductor technology scales down in size, process integration complexity and defects are increasing in 3D NAND flash, partially due to larger stack deposits and thickness variability between the wafer […]
February 4, 2019
Wedge Cutaway and Schematic – 3D NAND Device

Innovative Solutions to Increase 3D NAND Flash Memory Density

3D NAND flash memory has enabled a new generation of non-volatile solid-state storage useful in nearly every electronic device imaginable. 3D NAND can achieve data densities exceeding those of 2D NAND […]
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