December 14, 2021
A digital twin is a digital representation of a real-world item, and includes software objects or models that represents these real-world items. In MEMS product development, digital twins (or software […]
November 16, 2020
When they were first commercialized at the 22 nm node, finFETs represented a revolutionary change to the way we build transistors, the tiny switches in the “brains” of a chip. As […]
August 24, 2020
Understanding Advanced Packaging Technologies and Their Impact on the Next Generation of Electronics
Chip packaging has expanded from its conventional definition of providing protection and I/O for a discrete chip, to encompassing a growing number of schemes for interconnecting multiple types of chips. […]
June 26, 2020
Lam Research® is one of the top equipment suppliers in the semiconductor ecosystem. As a trusted, collaborative partner to the world’s leading semiconductor companies, Lam Research is a fundamental enabler […]
April 15, 2020
The IEEE MEMS conference was held in Vancouver during January 2020. We attended the conference to meet with our customers and to see what new developments are being made in […]
December 16, 2019
Semiconductor process engineers would love to develop successful process recipes without the guesswork of repeated wafer testing. Unfortunately, developing a successful process can’t be done without some work. This blog […]
July 31, 2019
Driven by Moore’s law, memory and logic semiconductor manufacturers pursue higher transistor density to improve product cost and performance [1]. In NAND Flash technologies, this has led to the market […]
May 21, 2019
As semiconductor technology scales down in size, process integration complexity and defects are increasing in 3D NAND flash, partially due to larger stack deposits and thickness variability between the wafer […]
February 4, 2019
3D NAND flash memory has enabled a new generation of non-volatile solid-state storage useful in nearly every electronic device imaginable. 3D NAND can achieve data densities exceeding those of 2D NAND […]
October 12, 2018
Unlike scaling practices in 2D NAND technology, the direct way to reduce bit costs and increase chip density in 3D NAND is by adding layers. In 2013, Samsung shipped the […]