Wafer-Level Process Modeling

Transistor-Level Performance Evaluation Based on Wafer-Level Process Modeling

By: Michael Hargrove, SP&I Engineer

Three years ago, I wrote a blog entitled “Linking Virtual Wafer Fabrication Modeling with Device-level TCAD Simulation” in which I described the seamless connection between the SEMulator3D® virtual wafer fabrication software platform and external 3rd party TCAD software. I’m now happy to report that device-level I-V performance analysis is now a built-in module within the SEMulator3D software platform.  Users are no longer required to export a mesh and import it into a TCAD platform, when performing transistor I-V simulation.  Now, once the 3D device structure is built in SEMulator3D, transistor I-V simulation can be performed directly within SEMulator3D without need for 3rd party solvers.  Contacts and bias can be applied using the SEMulator3D device design, and I-V transistor characteristics can be determined for specific steps in the process flow.  You can perform direct transistor-level performance evaluation inside the SEMulator3D software platform, without needing to export or import meshes. read more…

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