Videos
Watch our videos to learn about the latest advances in the semiconductor and MEMS industries, along with methods to address the most difficult challenges in technology development.
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Next Generation Transistor Technology
March 7, 2022
Nanosheets, or more generally, gate-all-around FETs (GAA FETs), mark the next big shift in transistor structures. David Fried, vice president of computational products at Lam Research, explains how these devices work and discusses the advantages of using these new types of transistors. During this discussion, David reviews numerous challenges that will be encountered in developing nanosheets and GAA FETs, including issues with metrology, design and process optimization. (Video Attribution: Semiconductor Engineering)
Design Technology Co-Optimization
January 18, 2022
Rising complexity is making it increasingly difficult to optimize chips for yield and reliability. Design Technology Co-Optimization (DTCO) is a technique used to accelerate the development of increasingly complex chips. In this video, David Fried (Vice President of Computational Products at Lam Research) describes how DTCO is being used to optimize the relationship between layout, design requirements and process flow, and discusses the overall benefits of DTCO. (Video Attribution: Semiconductor Engineering)
What’s Changing In DRAM
September 15, 2021
Most of the attention in chip scaling has been focused on logic and on-chip memory, but off-chip memory is starting to encounter problems, as well. This Semiconductor Engineering Tech Talk discusses the impact of shrinking features and increasing density, including variation, thermal effects and aging, as well as effects such as micro-loading and DRAM stacking. With David Fried, VP of computational products at Lam Research & Ed Sperling, Semiconductor Engineering. (Video Attribution: Semiconductor Engineering)
Virtual Fabrication At 7/5/3nm
October 23, 2020
David Fried, vice president of computational products at Lam Research, talks with Semiconductor Engineering about virtual fabrication at the most advanced nodes, how to create models using immature processes at new nodes, and how to fuse together data from multiple different silos. (Video Attribution: Semiconductor Engineering)
Full Stack Computational Optimization Through Virtual Fabrication
September 25, 2020
Design Technology Co-Optimization (DTCO) is used to optimize processes and design definitions early in technology development. It can predict layout-dependent process effects, improve yield, and help technologist avoid wrong technology paths. Unfortunately, DTCO is difficult to achieve in practice, due to fragmented software platforms, difficulties in matching levels of data abstraction, process depth variation, disparate physics and more. In this presentation, we will review a DTCO methodology to link design content with process technology that is computationally efficient, and can integrate various software platforms, levels of abstraction, process depths and other data required for full-stack DTCO. Explore more with Dr. Joseph Ervin, Director, Semiconductor Process & Integration of Lam Research’s talk at SEMICON Taiwan 2020.
Chip Challenges At 3/2nm
September 15, 2020
How to deal with variation, and interactions between various types of variation.
David Fried, vice president of computational products at Lam Research, talks with Semiconductor Engineering about issues at upcoming process nodes, the move to EUV lithography and nanosheet transistors, and how process variation can affect yield and device performance. (Video Attribution: Semiconductor Engineering)
Process Window Optimization
August 7, 2019
How to deal with variation, and interactions between various types of variation.
David Fried, vice president of computational products at Lam Research, examines increasing process variation and interactions between various types of variation, why different approaches are necessary to improve yield and continue scaling. (Video Attribution: Semiconductor Engineering)
Scaling Technology Nodes without Moving to New Transistor Architectures
June 24, 2019
David Fried, vice president of computational products at Lam Research, looks at shrinking tolerances at advanced processes, how that affects variation in semiconductor manufacturing, and what can be done to achieve the benefits of scaling without moving to new transistor architectures. (Video Attribution: Semiconductor Engineering)
MEMS Design Contest Interview with Final Winning Teams
September 6, 2018
MEMS Design Tools. In this video, members of the 1st and 2nd place winning teams from ESIEE, Sorbonne University and KAUST discuss lessons learned from their design work. The team members talk about their design ideas, their design workflow, challenges faced, and the benefits gained through their participation in the contest.
Design Flow and MEMS PDK Developed in Cooperation with XFAB
December 6, 2017
MEMS-based component suppliers want to rapidly ramp their designs into high-volume production. This demand is driving MEMS suppliers to focus on ways to more efficiently re-use established process steps, stacks and technology platforms.
In this webinar, you will learn about:
- The current state of the art in MEMS product design, including compact modeling, CMOS integration, MEMS PDKs and other innovative MEMS design flow techniques.
- New techniques to accelerate the MEMS design process and reduce silicon learning cycles at the foundry, through re-use of established process steps, stacks and technology platforms.
Problems and Solutions at 7nm
July 24, 2017
David Fried, vice president of computational products at Lam Research, has a discussion with Ed Sperling of Semiconductor Engineering about what’s going on at 7nm, and some of the problems that we’re starting to experience at both 7nm and 5nm. (Video Attribution: Semiconductor Engineering)
MEMS Design Contest Interview with Sally Ahmed of KAUST University
July 14, 2017
MEMS Design Tools. In this video, Sally Ahmed of KAUST University talks about her participation in the ongoing MEMS Design Contest. Sally explains how she became interested in the contest, describes her contest design, and discusses what she has learned through her participation in the contest.
Design and Optimize MEMS Devices with Coventor MEMS+ and Simulink
June 20, 2017
In this webinar, engineers from the MathWorks and Coventor present a streamlined workflow for designing and optimizing MEMS devices using MEMS+, MATLAB and Simulink.The webinar demonstrates this workflow on a MEMS accelerometer in force-feedback control to highlight the performance gains from this approach. (Video Attribution: MathWorks)
Demonstration of Coventor MEMS+®
MEMS+ is an industry-leading software tool used by engineers to design MEMS devices and integrate them into larger circuits and systems. Watch this video to gain a better understanding of how the tool works, its advantages over conventional finite element analysis tools, and how it works with tools such as MatLab Simulink® and Cadence Virtuoso®.
Quick Intro to Coventor MEMS+®
Coventor MEMS+ is a software environment for engineers who design MEMS and integrate MEMS with CMOS electronics and packaging. Learn how this powerful, innovative tool can accelerate your MEMS development project.