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Post-Doctoral R&D on Acoustic Modeling for MEMS – Paris, France

Post-Doctoral R&D on Acoustic Modeling for MEMS – Paris, France

Coventor, Inc. is the global market leader in design automation solutions for microelectromechanical systems (MEMS) and virtual fabrication of MEMS and semiconductor devices. Coventor serves a worldwide customer base of integrated device manufacturers, fabless design houses, independent foundries, and R&D organizations that develop MEMS-based products for automotive, aerospace, industrial, defense, and consumer electronics applications, including smart phones, tablets, wearables, and Internet of Things (IoT). Coventor’s software tools and expertise enable its customers to simulate and optimize MEMS device designs and fabrication processes, reducing reliance on time-consuming and costly build-and-test cycles.

We are searching for a talented PhD with a strong background in acoustic modeling.  You will apply your deep knowledge in acoustics or structural acoustics to develop modeling tools for micro-acoustic devices such as microphones, micro-speakers and ultrasonic transducers fabricated with MEMS technology. You will be a member of our software development team and participate in creating best-in-class, software products for MEMS design and simulation. You will work closely with our MEMS application engineers to understand the technical requirements of our partners and customers. Your work will enable Coventor and our European customers to solve the development challenges for the next generation of acoustic MEMS devices.

Responsibilities

  • Understand modeling requirements for acoustic MEMS devices such as microphones, micro-speakers, and ultrasonic transducers
  • Develop prototype modeling solutions for acoustic MEMS using Coventor’s software and/or third-party software
  • Interface and collaborate with our external research partners and customers
  • Collaborate with Coventor software development and application engineering teams towards implementing new modeling capabilities in future software releases
  • Draft user documentation and write technical papers
  • Prepare and present technical presentations on your work

Required Qualifications

  • PhD in engineering or physics, or latter stage of PhD studies
  • Strong theoretical understanding of acoustics, including use of lumped-parameter electrical circuit analogies
  • Proven ability to do analytical or semi-analytical modeling of acoustics problems
  • Experience in scripting in Matlab or Python
  • Excellent communication skills in English, both written and oral, as well as the ability to clearly communicate technical concepts

Desirable Qualifications

  • Any software development experience is a plus, preferably in C++ programming
  • Experience with numerical modeling tools such as circuit simulators or 3D field solvers.
  • Knowledge of structural acoustics

We offer an exciting position in a leading-edge advanced high-tech environment with many international contacts. The position is limited to a fixed term of two years and with the possibility of conversion to regular employment. This opening is located in Villebon-sur-Yvette, close to Paris. If you are interested in this opportunity and you are authorized to work in France, e-mail you resume in English to job1867@coventor.com.

Semiconductor Simulation Corporate Engineer – Waltham, MA.

Semiconductor Simulation Corporate Engineer – Waltham, MA

At Coventor Inc., we build innovative software products to solve semiconductor technology challenges. Our 3D modeling software is revolutionizing the way that semiconductor chips are fabricated around the world. Enabled by our core intellectual property – an accelerated 3D voxel modeling and visualization engine – our software is evolving fast as our business and customer base expands rapidly.

We are seeking a motivated, collaborative semiconductor simulation expert to be the internal expert on the behavior and simulation of semiconductor devices within the logic and memory semiconductor market. In this role you will have a unique opportunity to use your technical expertise to enable the roll-out of new device simulation software for leading semiconductor companies. You will use your expertise to collaborate with the software development group on the validity of the simulator and also create technical material to highlight the strengths and capabilities of the tools for our potential customers. You will be supported by our team of highly skilled, collaborative software engineers and semiconductor process and integration experts.

This is a technical position requiring an understanding of the physics governing cutting edge nanoscale device behavior in production today and in the near future such as FinFETs, nanowires, and 3D NAND flash.

Responsibilities:

  • Participate in the definition of product features and direction, in collaboration with the software engineering team
  • Contribute to software validation, product documentation, case studies, and technical publications
  • Work with the sales and marketing teams to launch and market new features
  • Educate the applications team on new product features

 

Required Qualifications (all of the following):

  • PhD in Electrical Engineering or equivalent
  • Deep understanding of semiconductor devices
  • 3+ years of professional experience in nanoscale device simulation for commercial production, particularly for logic and memory
  • Good verbal communication and writing skills

 

Desirable Qualifications (any of the following):

  • Professional experience in a software development organization
  • Professional experience in semiconductor process modeling
  • Working knowledge of MATLAB

 

This regular, full-time position is located in Waltham, MA. Coventor offers comprehensive benefits and is an EEO/AA Employer. You must be a current legal resident of the U.S. or have a valid U.S. visa to apply for this position. Please e-mail your resume to job1863@coventor.com.

About Coventor:

For more information about Coventor, our business, and our products, please visit us on
the web at http://www.coventor.com.

GPU Computing Software Engineer – Paris, France

GPU Computing Software Engineer – Paris, France

At Coventor, we build innovative software products to solve semiconductor technology challenges. Our 3D modeling software is revolutionizing the way that semiconductor chips are fabricated around the world. Enabled by our core intellectual property – an accelerated 3D voxel modeling and visualization engine – our software is evolving fast as our business and customer base expands rapidly.

We are searching for a talented software engineer with a strong background in GPU computing and rendering to join our development team. Our voxel-based 3D modeling engine creates highly accurate and topologically complex models of nanometer-scale semiconductor devices. Consequently, the accurate real-time visualization of such large structures across a variety of hardware platforms is a major challenge. You will participate in the development of a GPU-based ray-tracing engine for complex voxel models, in the implementation of advanced data visualization techniques, as well as in the implementation of other general-purpose computing algorithms on the GPU.

This is a perfect role for candidates who are interested in GPU computing, ray-tracing, 3D computer graphics as well as software engineering in a commercial environment. You will work closely with our semiconductor process technology team to understand technical requirements of our partners and customers. Your work will enable Coventor and our customers to visualize and inspect the highly complex 3D structures of today’s semiconductor devices in real time.

Responsibilities

  • Participate in the development of a GPU-based real-time ray-tracing engine for complex 3D voxel models
  • Implement advanced 3D data visualization algorithms
  • Accelerate voxel model operations, numerical linear algebra functions, or geometry processing algorithms
  • Collaborate with our applications team to understand and troubleshoot customer requests and problems
  • Create high-quality software including unit tests and documentation

Required Qualifications

  • PhD or MS in computer science related to GPU computing, computer graphics, or equivalent experience
  • Expertise in GPU computing, ray-tracing, level-of-detail techniques, handling of large data sets on the GPU
  • In-depth knowledge of one or more GPU computing toolkits such as NVIDIA® CUDA™, OpenCL™, or Vulkan®
  • Strong background in C++ programming and software engineering
  • Strong fundamental math skills
  • Excellent communication skills in English, both written and oral, as well as the ability to clearly communicate technical concepts

Desirable Qualifications

  • Familiarity with multiple GPU computing toolkits on different platforms is a plus
  • Experience with GPU performance profiling and debugging tools
  • Experience with voxel modeling and/or geometry processing algorithms
  • Knowledge of agile methods, object-oriented design, design patterns, and cross-platform development (Windows/Linux)
  • Experience with C++ libraries such as boost, STL, or Qt. Familiarity with C++11 and template programming. Python coding skills.
  • Any professional software development experience is a plus, preferably developing a 3D modeling software product
  • Knowledge of semiconductor process technology, or any software related to semiconductor design or manufacturing

Salary, job title, and responsibilities will be commensurate with experience. This opening is in Villebon-sur-Yvette, close to Paris, or in Dublin, Ireland. If you are interested in this opportunity and you are authorized to work in France or Ireland, e-mail you resume in English to job1866@coventor.com.

Unlikely Pairings – Recent Atypical Mergers

By Bryon Moyer

Companies come; companies go. I don’t focus a lot on who buys whom – there are plenty of folks breathlessly watching that stuff, so I mostly leave the drama to them. After all, it’s an age of consolidation and accumulation of immense corporate power. So your typical low- to mid-level merger may not be particularly noteworthy.

But lately, there have been a couple of mergers/acquisitions that have had some unusual features to them. Add to that the fact that they’re companies we’ve looked at before, and it seems worth spending some time on them.

read the full article here.

Delivering the Next 5 Years of Semiconductor Technology

New, advanced semiconductor processing and architectural technologies take years to perfect and put into production. In the meantime, semiconductor customers continue to demand faster, smaller and higher functioning devices. Semiconductor manufacturers need to decide whether (and when) to jump to the next generation of devices and production technologies, weighing the risk and benefit of bringing the next processing and architecture technologies to market.

A recent example of this type of risk analysis can be found in the gradual plans by foundries to adopt EUV technology. EUV technologies will reduce current requirements for multi patterning and (eventually) improve yields. However, EUV technology has many technological hurdles, including mask defects, CD uniformity, and production rate and yield issues. Billions of dollars have been invested in EUV development, yet no foundry is currently using the technology in production.

Could we extend existing technology concepts to deliver the next generations of semiconductor scaling, and avoid or defer the risk of jumping to next generation device and production technologies? Or, does the industry need paradigm-shifting technologies to reach these goals? Is there a way that we squeeze additional angstroms out of existing process and technology elements? Can we use variation reduction and process control to create the next few generations of semiconductor scaling? Or, do we simply need entirely new processes and architectures to reach these difficult goals?

There might be an entire node of scaling available from variation reduction, with numerous opportunities for variation reduction in advanced technology development. Our ability to detect, measure and characterize variability issues will be critical in variation reduction, along with process optimization and co-optimization strategies and challenges. Process controls are a key factor in being able to reduce process variability and to scale effectively.

If you are interested in exploring this topic further, we invite you to attend a complimentary seminar sponsored by Coventor in San Francisco on December 5, 2017, entitled “Everything is Under Control:  Delivering the Next 5 Years of Semiconductor Technology”. The seminar will be moderated by Ed Sperling, Editor in Chief of Semiconductor Engineering. Leading semiconductor industry panelists will discuss alternative methods to solve fundamental problems of technology scaling, and review techniques and strategies that might extend the lifetime of the latest technologies and propel us into the future. They will explore the latest advances in semiconductor architectures, patterning, metrology, advanced process control, co-optimization and integration. If you are unable to attend the seminar, keep your eye on future issues of Semiconductor Magazine to view a summary of the discussion.

To pre-register for the complimentary panel discussion, click here.

SEMulator3D Honored as UBM ACE Award Finalist

For Immediate Release
For more information, contact:
Toni Sottak
(408) 876-4418
toni@wiredislandpr.com

SEMulator3D Honored as UBM ACE Award Finalist

Coventor’s Virtual Fabrication Platform Recognized for Significantly Improving Electronics Manufacturing

CARY, NC– November 17, 2017 – Coventor®, Inc. a Lam Research Company and leading supplier of virtual fabrication solutions for semiconductor and micro-electromechanical systems (MEMS) devices, today announced its 3D virtual fabrication platform, SEMulator3D®, has been named a finalist in UBM’s annual ACE Awards competition.

The ACE (Annual Creativity in Electronics) Awards, in partnership with EE Times and EDN, showcase the best of the best in today’s electronics industry, including the hottest new products, start-up companies, design teams, executives, and more. ACE finalists and winners are hand selected by a panel of EE Times and EDN editors as well as independent judges from the across the industry. read more…

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Overlay Challenges On The Rise

By MARK LAPEDUS

The overlay metrology equipment market is heating up at advanced nodes as the number of masking layers grows and the size of the features that need to be aligned continue to shrink.

Both ASML and KLA-Tencor recently introduced new overlay metrology systems, seeking to address the increasing precision required for lines, cuts and other features on each layer. At 10/7nm, there may be 80 or more masking layers, versus 40 at 28nm. And if those layers are not precisely measured, the features being patterned, deposited and etched may not line up from one layer to the next.

read the full article here.

Technical Tidbits from IWLPC and MSEC 2017

By Francoise von Trapp

It’s been a busy few weeks for me as I attended both the International Wafer Level Packaging Conference (IWLPC), October 24-26, 2017 at the DoubleTree in San Jose and SEMI-MSIG’s MEMS and Sensors Executive Congress, October 31-Nov. 2, at the Hayes Mansion in San Jose. In addition to taking in some great keynotes and technical sessions, I had the opportunity to meet with several companies to find out what’s new.

read the full article here.