Noise Modeling for MEMS Microphones

By: Chris Welham, Senior Manager, MEMS Applications Engineering

A Section of a MEMS Microphone Model


Here at Coventor, we are seeing a lot of interest in simulating noise, particularly for condenser microphones. With any transducer noise reduction is always a plus, and with microphones there are two specific applications that need low noise. One is where the microphone is positioned away from the sound source, such as in video calling or when using voice commands with tablet computers. The other is where multiple microphones are positioned in an array, to detect the direction of incoming sound or for noise canceling applications.

Noise Sources in MEMS Microphones

All microphones generate noise, in the electronics, the package and the sensing element itself. In a MEMS condenser microphone the noise of the sensing element is dominated by thermal noise (also referred to as Johnson-Nyquist noise) created by the flow resistances of the sound port, back plate perforation holes and diaphragm vent holes. Physically, the origin of the thermal noise is the random motion of the molecules of air associated with these the flow resistances. The molecules of air generate movement of the diaphragm which is converted to an electrical signal by an electronic circuit. In practice, the level of noise generated is closely linked to the sensitivity of the microphone: less noise comes at the expense of a lower sensitivity and vice-versa. For this reason, the Signal to Noise ratio (SNR) provides a good indication of performance. The SNR is the difference in decibels between the noise level and the sensitivity under a 1 kHz, 94 dB SPL (1 Pa) reference signal.

Designing MEMS Microphones

MEMS condenser microphones are quite challenging devices to model. In most cases you have non-linear coupled physics to deal with, and complex geometry in the highly perforated back plate. The conventional approach is to linearize the system and use an equivalent circuit model. This approach works, though it requires a high level of modelling expertise, often to the Ph.D. level, to create and maintain the model. Here’s a thought. Rather than build an equivalent circuit model why not just simulate the SNR directly? All you need is to have is the right mix of elements and simulator to do the job. For those not already using the MEMS+® module of CoventorMP™, hopefully you’ll be interested to know we’ve had this capability for a number of years using our integration with Cadence Spectre®. With the next MEMS+ module of CoventorMP due out in Spring 2018, you will also be able run a noise analysis using the MEMS+ simulator. We are really proud of this new leading edge simulation capability for MEMS device designers.

To understand how our solution works, please take a look at the diagram below. This shows a hybrid condenser microphone model. The membrane and back plate are modeled using our multi‑physics finite elements. Lumped elements are used for the vent hole, back-chamber and the sound port. If you’re only looking at the sensing element (i.e. no attached electronics) you can directly run a simulation in MEMS+ and/or MathWorks MATLAB®.

Diagram showing MEMS+ hybrid model comprising distributed finite elements and lumped elements. All dissipative elements act as thermal noise sources.

Using either tool, you can predict the sensitivity and noise of any output field. For noise, this could be displacement noise, or more usually capacitance noise. The latter can be easily converted into a voltage noise and then integrated across the audio band with an A-weighting filter. Then, it’s a simple step to combine the noise with the sensitivity to get the SNR value.

Of course, you might want to go a step further and model the electronics with the sensing element of microphone using Cadence Virtuoso®. Here, for example, you can add a constant-charge bias circuit and run the sensitivity and noise analysis in Cadence Spectre®. The SNR can be computed using the Cadence Virtuoso Calculator®. Incidentally, you are also only a few clicks (and a few minutes) away from predicting Total Harmonic Distortion (THD) too.

Cadence Virtuoso schematic with ¼ microphone model, displaying calculated sensitivity, noise, SNR and THD

If you would like to know more, then please feel free to contact us for a demonstration. We’re also keen to hear of any simulation problem that you have – perhaps we can help out?

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Comparing MEMS and the RMS Titanic: Some Thoughts from the IEEE MEMS 2018 Conference

By: Chris Welham, Sr. Manager, MEMS Applications Engineering

Conference dinner view of the life-size outlines of the Titanic and Olympic main deck’s, illuminated by blue light

How are MEMS and Large Ships Alike?

MEMS 2018 was held in Belfast, Northern Ireland this year, on the site where the RMS Titanic was built. On exhibit was the SS Nomadic, a tender used to transfer mail and passengers to the RMS Titanic and her sister ship RMS Olympic. Passing by the SS Nomadic on the way to the conference dinner, I noticed the riveted plates from which the tender was built. These riveted plates reminded me of the finite element plate models used in the MEMS+ module of CoventorMP, which can also be joined to other elements using “connectors” or “nodes” rather than rivets.

I wondered what other components in MEMS+ existed in the Titanic? For sure, perforated plates, or baffles. Many MEMS devices use perforated plates, either to aid the release etch in fabrication or for reasons of operation. Release etch, and the effects of pattern dependence, are key fabrication processes modeled in our virtual fabrication tool, SEMulator3D. A condenser microphone, which can be modeled using MEMS+, has at least one perforated back plate. Steel beams, too? Certainly, MEMS+ has Timoshenko Beam models, the underlying theory of which was first developed by Stephen Timoshenko just before the Titanic sank. Further comparison was harder. Comb capacitors? Well only as tuning condensers in the on-board Marconi Wireless Set, as it was then known. Fluid dampers? Perhaps in the engine supports of the SS Nomadic to reduce vibration.

What happened at the IEEE MEMS Conference?

Back to the conference, there was a wide range of interesting presentations and posters. Topics covered ranged from inertial sensors, actuators, acoustics, resonators and RF MEMS (all areas where we specialize), through to material science and microfluidics. It was good to see our tools being used to simulate a range of MEMS devices. We also had the opportunity to discuss emerging research in the area of MEMS simulation, which is always important for us to follow to ensure that our tools retain their leading edge capabilities.

What’s New with CoventorMP?

Incidentally, there are exciting new features for microphone design in the upcoming CoventorMP release, due out this Spring. We’re also expanding our capabilities for modeling suspension beams as well as lots of other new features. More to follow on these exciting enhancements as we get closer to the release date!


By Mike Pinelis

In August of 2017, Lam Research completed the acquisition of Coventor, a MEMS modeling and simulation software company, for a total purchase consideration of $137.6 million. When asked about how Coventor fits into Lam’s portfolio, the company’s Executive VP and CFO Douglas Bettinger said that, potentially, there are benefits and synergies with Coventor’s software capability to model and simulate the actual output of Lam’s equipment. We recently spoke with Stephen Breit, Coventor’s Sr. Director of MEMS, and discussed the trends that he is seeing in the MEMS marketplace. Since Coventor works with many MEMS companies, we also asked Stephen about the notable startups and technologies.

read the full article here.

Future Outlook: The Advantages of Fully Depleted Silicon on Insulator (FD-SOI) Technology

By: Michael Hargrove, SP&I Engineer

If my memory serves me well, it was at the 1989 Device Research Conference where the potential merits of SOI (Silicon on Insulator) technology were discussed in a heated evening panel discussion. At that panel discussion, there were many advocates for SOI, as well as many naysayers. I didn’t really think more about SOI technology until the mid-nineties, when I was sitting in a meeting where the first SOI device data was being presented in the hallowed halls of IBM. The data was incredibly scattered and my thinking was “this technology is going nowhere!” The purported performance advantage was stated to be ~35%, simply due to the capacitance reduction (no longer did the bottom junction capacitance play a role) and the speed advantages of stacked devices in a NAND circuit. It all sounded great, but in the mid-nineties, the data simply didn’t support it. Nonetheless, the SOI advocates pursued their beloved technology, and the rest is history. SOI technology has been part of IBM’s main stream high-performance technology base through the 14nm node, including FinFETs on SOI. read more…

What the Experts Think: Delivering the Next 5 Years of Semiconductor Technology

Coventor recently sponsored an expert panel discussion at IEDM 2017 to discuss how we might advance the semiconductor industry into the next generation of technology.  The panel discussed alternative methods to solve fundamental problems of technology scaling, using advances in semiconductor architectures, patterning, metrology, advanced process control, variation reduction, co-optimization and new integration schemes.  Our panel included Rick Gottscho, CTO of Lam Research; Mark Dougherty, vice president of advanced module engineering at GlobalFoundries; David Shortt, technical fellow at KLA-Tencor; Gary Zhang, vice president of computational lithography products at ASML; and Shay Wolfling, CTO of Nova Measuring Instruments.

The Next 5 Years of Semiconductor Technology

L-R: Ed Sperling (moderator), Shay Wolfling, Rick Gottscho, Mark Dougherty, Gary Zhang, David Shortt

Here are a few expert predictions for the next 5 years of semiconductor technology that came out of the discussion:

FinFETs will get extended to at least to 5nm, and possibly 3nm

Rick Gottscho of Lam Research felt that FinFETs will get extended to at least 5nm, and possibly 3nm.    Shay Wolfing of Nova Measuring Instruments predicted that nanosheet technology could be used after FinFET extensions would not scale further.

EUV will be used at new nodes, followed by High NA Lithography

Gary Zhang of ASML stated that EUV will drive lithography at new nodes, with high-NA as an extension to EUV on the technology roadmap. Gary felt that managing the complexity and the cost of these new lithography techniques will be challenging, but feasible.

Materials and basic structures may diverge by supplier, at 7 nm and beyond

Mark Dougherty of GlobalFoundries noted that suppliers may not align at the end of the day on the same materials and basic structures to scale semiconductor technology. It’s possible that there might be some divergence, such as in back-end-of-line metallurgy.

Metrology can meet future technical challenges, but inspection and measurement costs may rise

Gary Zhang confirmed that 3D measurements below an angstrom are now possible, and that we have metrology solutions available for the near future.   David Shortt of KLA-Tencor asserted that end-to-end cycle time and cost are increasing for inspection and metrology, and that these trends may continue unless technical risk reduction is started early in the development process.

3D NAND technology will continue scaling beyond the existing 48 layer structures

Rick Gottscho stated that he sees a path over the next 10 years to scale 3D NAND manufacturing technology, up to 256 layers.   Rick had some concerns over film stress and challenging etch requirements in meeting this scaling projection.

If you are interested in reading more about this panel, you can find the first part of the panel transcript at Semiconductor Engineering.   Future articles in Semiconductor Engineering will highlight the remainder of the panel discussion, including the expert’s views on the role of advanced process control, variation reduction, co-optimization and new integration schemes in delivering the next 5 years of semiconductor technology.

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Post-Doctoral R&D on Acoustic Modeling for MEMS – Paris, France

Post-Doctoral R&D on Acoustic Modeling for MEMS – Paris, France

Coventor, Inc. is the global market leader in design automation solutions for microelectromechanical systems (MEMS) and virtual fabrication of MEMS and semiconductor devices. Coventor serves a worldwide customer base of integrated device manufacturers, fabless design houses, independent foundries, and R&D organizations that develop MEMS-based products for automotive, aerospace, industrial, defense, and consumer electronics applications, including smart phones, tablets, wearables, and Internet of Things (IoT). Coventor’s software tools and expertise enable its customers to simulate and optimize MEMS device designs and fabrication processes, reducing reliance on time-consuming and costly build-and-test cycles.

We are searching for a talented PhD with a strong background in acoustic modeling.  You will apply your deep knowledge in acoustics or structural acoustics to develop modeling tools for micro-acoustic devices such as microphones, micro-speakers and ultrasonic transducers fabricated with MEMS technology. You will be a member of our software development team and participate in creating best-in-class, software products for MEMS design and simulation. You will work closely with our MEMS application engineers to understand the technical requirements of our partners and customers. Your work will enable Coventor and our European customers to solve the development challenges for the next generation of acoustic MEMS devices.


  • Understand modeling requirements for acoustic MEMS devices such as microphones, micro-speakers, and ultrasonic transducers
  • Develop prototype modeling solutions for acoustic MEMS using Coventor’s software and/or third-party software
  • Interface and collaborate with our external research partners and customers
  • Collaborate with Coventor software development and application engineering teams towards implementing new modeling capabilities in future software releases
  • Draft user documentation and write technical papers
  • Prepare and present technical presentations on your work

Required Qualifications

  • PhD in engineering or physics, or latter stage of PhD studies
  • Strong theoretical understanding of acoustics, including use of lumped-parameter electrical circuit analogies
  • Proven ability to do analytical or semi-analytical modeling of acoustics problems
  • Experience in scripting in Matlab or Python
  • Excellent communication skills in English, both written and oral, as well as the ability to clearly communicate technical concepts

Desirable Qualifications

  • Any software development experience is a plus, preferably in C++ programming
  • Experience with numerical modeling tools such as circuit simulators or 3D field solvers.
  • Knowledge of structural acoustics

We offer an exciting position in a leading-edge advanced high-tech environment with many international contacts. The position is limited to a fixed term of two years and with the possibility of conversion to regular employment. This opening is located in Villebon-sur-Yvette, close to Paris. If you are interested in this opportunity and you are authorized to work in France, e-mail you resume in English to

Semiconductor Simulation Corporate Engineer – Waltham, MA.

Semiconductor Simulation Corporate Engineer – Waltham, MA

At Coventor Inc., we build innovative software products to solve semiconductor technology challenges. Our 3D modeling software is revolutionizing the way that semiconductor chips are fabricated around the world. Enabled by our core intellectual property – an accelerated 3D voxel modeling and visualization engine – our software is evolving fast as our business and customer base expands rapidly.

We are seeking a motivated, collaborative semiconductor simulation expert to be the internal expert on the behavior and simulation of semiconductor devices within the logic and memory semiconductor market. In this role you will have a unique opportunity to use your technical expertise to enable the roll-out of new device simulation software for leading semiconductor companies. You will use your expertise to collaborate with the software development group on the validity of the simulator and also create technical material to highlight the strengths and capabilities of the tools for our potential customers. You will be supported by our team of highly skilled, collaborative software engineers and semiconductor process and integration experts.

This is a technical position requiring an understanding of the physics governing cutting edge nanoscale device behavior in production today and in the near future such as FinFETs, nanowires, and 3D NAND flash.


  • Participate in the definition of product features and direction, in collaboration with the software engineering team
  • Contribute to software validation, product documentation, case studies, and technical publications
  • Work with the sales and marketing teams to launch and market new features
  • Educate the applications team on new product features


Required Qualifications (all of the following):

  • PhD in Electrical Engineering or equivalent
  • Deep understanding of semiconductor devices
  • 3+ years of professional experience in nanoscale device simulation for commercial production, particularly for logic and memory
  • Good verbal communication and writing skills


Desirable Qualifications (any of the following):

  • Professional experience in a software development organization
  • Professional experience in semiconductor process modeling
  • Working knowledge of MATLAB


This regular, full-time position is located in Waltham, MA. Coventor offers comprehensive benefits and is an EEO/AA Employer. You must be a current legal resident of the U.S. or have a valid U.S. visa to apply for this position. Please e-mail your resume to

About Coventor:

For more information about Coventor, our business, and our products, please visit us on
the web at

GPU Computing Software Engineer – Paris, France

GPU Computing Software Engineer – Paris, France

At Coventor, we build innovative software products to solve semiconductor technology challenges. Our 3D modeling software is revolutionizing the way that semiconductor chips are fabricated around the world. Enabled by our core intellectual property – an accelerated 3D voxel modeling and visualization engine – our software is evolving fast as our business and customer base expands rapidly.

We are searching for a talented software engineer with a strong background in GPU computing and rendering to join our development team. Our voxel-based 3D modeling engine creates highly accurate and topologically complex models of nanometer-scale semiconductor devices. Consequently, the accurate real-time visualization of such large structures across a variety of hardware platforms is a major challenge. You will participate in the development of a GPU-based ray-tracing engine for complex voxel models, in the implementation of advanced data visualization techniques, as well as in the implementation of other general-purpose computing algorithms on the GPU.

This is a perfect role for candidates who are interested in GPU computing, ray-tracing, 3D computer graphics as well as software engineering in a commercial environment. You will work closely with our semiconductor process technology team to understand technical requirements of our partners and customers. Your work will enable Coventor and our customers to visualize and inspect the highly complex 3D structures of today’s semiconductor devices in real time.


  • Participate in the development of a GPU-based real-time ray-tracing engine for complex 3D voxel models
  • Implement advanced 3D data visualization algorithms
  • Accelerate voxel model operations, numerical linear algebra functions, or geometry processing algorithms
  • Collaborate with our applications team to understand and troubleshoot customer requests and problems
  • Create high-quality software including unit tests and documentation

Required Qualifications

  • PhD or MS in computer science related to GPU computing, computer graphics, or equivalent experience
  • Expertise in GPU computing, ray-tracing, level-of-detail techniques, handling of large data sets on the GPU
  • In-depth knowledge of one or more GPU computing toolkits such as NVIDIA® CUDA™, OpenCL™, or Vulkan®
  • Strong background in C++ programming and software engineering
  • Strong fundamental math skills
  • Excellent communication skills in English, both written and oral, as well as the ability to clearly communicate technical concepts

Desirable Qualifications

  • Familiarity with multiple GPU computing toolkits on different platforms is a plus
  • Experience with GPU performance profiling and debugging tools
  • Experience with voxel modeling and/or geometry processing algorithms
  • Knowledge of agile methods, object-oriented design, design patterns, and cross-platform development (Windows/Linux)
  • Experience with C++ libraries such as boost, STL, or Qt. Familiarity with C++11 and template programming. Python coding skills.
  • Any professional software development experience is a plus, preferably developing a 3D modeling software product
  • Knowledge of semiconductor process technology, or any software related to semiconductor design or manufacturing

Salary, job title, and responsibilities will be commensurate with experience. This opening is in Villebon-sur-Yvette, close to Paris, or in Dublin, Ireland. If you are interested in this opportunity and you are authorized to work in France or Ireland, e-mail you resume in English to