Imec researchers using Coventor’s SEMulator3D platform to model and optimize 7nm manufacturing technology
LEUVEN, Belgium & CARY, North Carolina – October 28, 2014 – Belgian nanoelectronics research center imec has announced a joint development project with Coventor, a leading supplier of semiconductor process development tools. The collaboration will enable faster and more optimized development of advanced manufacturing technology in the 3D device architecture era, extending down to imec’s 10- and 7-nanometer (nm) processes.
By Steve Breit, V.P. Engineering
I’ve been doing a lot of interviewing over the last 6 months as we grow our engineering team. I often say that hiring is the most important part of my job and also the hardest part. Like any sensible technology company, Coventor wants to hire the best engineers we can find. Good engineers love engineering. They love to build, to create, to innovate, to solve problems. Good engineers are methodical and persistent, but also bring engineering judgment and intuition that helps them arrive at solutions efficiently. Good engineers can’t help doing engineering – it’s who they are. Over the years, I’ve observed that good engineers are way more productive than mediocre engineers. The difference in productivity can be astounding, in excess of 2 or 3X for the best engineers. The trick, at least during the hiring process, is to discern which candidates are the good engineers. You can’t just look at academic degrees, skills claimed, or work experience to tell the difference. read more…
by Paul McLellan, SemiWiki
One of the things about MEMS devices is that they almost always live on a chip that also contains the electronics necessary to process the output from the sensor. For example, an on-chip accelerometer for a car airbag deployment will contain the electronics necessary to process the signal from the sensor and end up with something much closer to “we’re crashing, deploy the airbags” versus “we’re OK, don’t fire off the airbags.”
The design of the MEMS devices themselves are typically done with some form of finite-element analysis (FEA), a very general approach to designing mechanical structures. However, these models of the device are very complex and slow to evaluate due to the huge number of degrees of freedom. This is fine for designing the device itself but for working with the electronics a simpler model of the device is required that is accurate enough for the purpose but is also fast to evaluate.
By Ryan Patz, Applied Materials
NAND Flash memory has become the driver of semiconductor technology and the four primary manufacturers are pushing hard to continue scaling in order to preserve margins. Smartphone growth continues to increase demand and revenue close to $30 Billion is expected for 2014. 3D NAND is not quite ready for “prime time” so significant effort is required to resolve current 2D limitations to enable 1x nm devices. The main process integration challenges include patterning the very small features (often employing quadruple spacer patterning technology), fill issues due to aspect ratios >10 and cell to cell interference .
By Francoise von Trapp
3D In-Depth, EDA Tools
I don’t usually write about MEMS. But every once in a while, when MEMS (stands for micro-electromechanical systems) touches anything to do with 3D integration, usually at the system-level, I might veer slightly out of my comfort zone to interview a MEMS supplier about their latest developments. I find it’s a good way to learn about the synergies and to cross-pollinate information. Today was one of those days. I interviewed Steve Breit, PhD, VP of Engineering, Coventor, supplier of design automation software for MEMS and semiconductor applications. Breit reminded me that through silicon via technology (TSV), which is critical for 3D IC, owes a debt to MEMS. He’s right about that. So I figure a nod to MEMS now and again on 3D InCites isn’t out of place.
Breit briefed me on the company’s latest version of its MEMS+ modeling environment for accelerated development of advanced MEMS devices and systems, and what the improvements mean for ASIC designers who need to integrate MEMS devices into their system design.
Gunar Lorenz, PhD
Director, System Level Simulation
We just rolled out MEMS+ 5.0 with lots of new capabilities for our users. I discussed some of the new features, support of scanning mirrors in particular, in a previous post. This time I would like to focus on the new capabilities for exporting reduced order models (ROMs) of MEMS devices that system engineers can place in their Simulink schematics and IC designers can place in their circuit schematics.
Before getting into the technical stuff, allow me to provide some motivation. To design the control and signal processing electronics that go around every MEMS device, system engineers usually work in Simulink while circuit designers work in schematic entry tools such as Cadence Virtuoso. There’s a MEMS block in their flow diagram or schematic with an underlying model that captures the coupled electromechanical behavior of the MEMS device. It’s common practice to “hand craft” the MEMS behavioral model, but hand crafted models have many shortcomings: they’re usually over simplified, capturing only one degree of freedom and omitting nonlinear effects. Furthermore, it’s difficult to keep hand crafted models in sync with evolving device designs. All of these shortcomings can be avoided by using ROMs exported from MEMS+ instead of hand-crafted models.