Quality Assurance Engineer for 3D Semiconductor Modeling Software – Waltham, MA
We are seeking an entry-level engineer with a strong interest in 3D modeling and simulation to perform quality assurance on our advanced semiconductor fabrication modeling and electrical analysis software. You will be embedded in a collaborative software development team that is following the Scrum agile development process. Through daily engagement with the developers, you will play a critical role in helping us deliver quality software on both Windows and Linux platforms. Your title and salary will be commensurate with your education and experience.
- Validate the functionality and accuracy of our semiconductor virtual fabrication environment
- Participate in planning and design discussions with the software development team
- Collaborate with software developers to isolate and resolve defects
- Conduct exploratory testing by developing realistic process flows representing advanced CMOS technology nodes
- Design test cases for automated functional and performance regression test suites
- Numerically verify transistor-level electrical analysis solvers
- Interact with the applications support team to define customer-centric test cases
- BS in Electrical Engineering, Computer Engineering, Computer Science or a related discipline
- 0-2 years of relevant engineering experience
- Detail-oriented individual who enjoys systematically exploring engineering software
- Proficiency in Python or similar scripting language
- Proficiency with Windows and Linux operating systems
- Team oriented personality with excellent interpersonal skills
- Excellent English communication skills (verbal and written)
Desirable Qualifications (any of the following):
- Semiconductor technology and processing education and/or experience
- Work experience in software quality assurance
- Experience as a user or tester of 3D software such as CAD, CAE or TCAD tools
This regular, full-time position is located in Waltham, MA. Coventor offers comprehensive benefits and is an EEO/AA employer. You must be a current legal resident of the U.S. or have a valid U.S. visa to apply for this position. Please e-mail your cover letter and resume to email@example.com.
Coventor, Inc. (www.coventor.com) is the global market leader in virtual fabrication solutions for semiconductor technologies and design automation solutions for microelectromechanical systems (MEMS). Coventor serves a worldwide customer base of integrated device manufacturers, independent foundries, equipment makers, and R&D organizations that develop semiconductor and MEMS technologies for consumer, automotive, aerospace, industrial, and defense uses. Coventor’s predictive modeling tools and expertise enable its customers to dramatically reduce silicon learning cycles, giving them a time-to-market advantage and reducing technology development costs. The company is headquartered in Cary, NC and has offices in Waltham, MA, Silicon Valley CA, and Paris, France.
By: Daniel Sieger, Lead Engineer, SEMulator3D Geometry and Michael Hargrove, Semiconductor Process & Integration Engineer
The SEMulator3D software platform has once again been updated and improved with significantly more features, making it the industry leader in semiconductor virtual fabrication. read more…
By Mark Lapedus
Semiconductor Engineering sat down to discuss the foundry business, memory, process technology, lithography and other topics with David Fried, chief technology officer at Coventor, a supplier of predictive modeling tools. What follows are excerpts of that conversation.
SE: Chipmakers are ramping up 16nm/14nm finFETs today, with 10nm and 7nm finFETs just around the corner. What do you see happening at these advanced nodes, particularly at 7nm?
Fried: Most people are predicting evolutionary scaling from 14nm to 10nm to 7nm. It’s doubtful that we will see anything really earth-shattering in these technologies. And so, a lot of the challenges come down to patterning. We are going to see multi-patterning schemes really take hold at more levels. For example, the fins are now based on self-aligned double patterning. People will move into self-aligned quad patterning. The gates are maybe self-aligned double. Now, they will move into self-aligned quad. So, that’s going to be a big expense, because each level is going to have multiple passes and multiple cuts.
read the full article here
Tagged 10NM, 3D NAND, 5NM, ATOMIC-LEVEL VARIABILITY, BEOL, Coventor, DEPOSITION, Directed Self Assembly, DSA, ETCH, EUV, III-V MATERIALS, INTEL, lithography, LOW-K DIELECTRICS, MRAM, multi-patterning, NANOWIRE FETS, RC DELAY, RERAM, SADP, TSMC
By: Stephen Breit, VP of Engineering
I recently gave an invited talk at the IEEE Inertial Sensors 2016 symposium that discussed the future of commodity MEMS inertial sensor design and manufacturing. Inertial sensors comprise one of the fastest growing and most successful segments of the MEMS market. read more…
By: Mattan Kamon, PhD., Distinguished Technologist, R&D, Coventor
But first, more generally, will directed self-assembly (DSA) join Extreme Ultraviolet (EUV) Lithography and next generation multi-patterning techniques to pattern the next memory and logic technologies? Appealing to the wisdom of crowds, the organizers of the 2015 1st International DSA symposium recently surveyed the attendees, and nearly 75% believed DSA would insert into high volume manufacturing within the next 5 years, and nearly 30% predicted insertion within the next 2 years. What is gating insertion? The crowd rated defectivity as the most critical issue facing DSA. This fact adds weight to memory being the first to be patterned with DSA. This is because, as Roel Gronheid from IMEC pointed out last month at the SPIE Advanced Lithography conference , memory chips can tolerate single failing cells through redundancy and so can could tolerate higher defectivity in patterning (roughly 1 defect/cm2 compared to 0.01 defect/cm2 for logic). Defectivity rates for DSA aren’t there yet (according to public information), but are rapidly approaching , . read more…
Tagged 14 nm DRAM process modeling, Directed Self Assembly, DSA, LER, LWR, Process Modeling, Process Simulation, SAQP, Self-Aligned Quadruple Patterning, semiconductor process modeling, Semiconductor Process Simulation, virtual fabrication
By Mark Lapedus
The multi-beam e-beam mask writer business is heating up, as Intel and NuFlare have separately entered the emerging market.
In one surprising move, Intel is in the process of acquiring IMS Nanofabrication, a multi-beam e-beam equipment vendor. And separately, e-beam giant NuFlare recently disclosed its new multi-beam mask writer technology.
As a result of the moves, the Intel/IMS duo and NuFlare will now race each other to bring multi-beam mask writers into the market. Still in the R&D stage, these newfangled tools promise to speed up the write times for next-generation photomasks, although there are still challenges to bring this technology into production.
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Tagged ASML, Coventor, D2S, DNP, EUV, EUV RESISTS, GLOBALFOUNDRIES, ILT, IMS, INPRIA, INTEL, INVERSE LITHOGRAPHY TECHNOLOGY, JEOL, KLA-TENCOR, LAM RESEARCH, MENTOR GRAPHICS, Moore's Law, MULTI-BEAM E-BEAM, MULTI-BEAM MASK WRITING, NANOFABRICATION, NUFLARE, OPC, OPTICAL PROXIMITY CORRECTION, PHOTOMASKS, PHOTONICS, RET, RETICLE ENHANCEMENT TECHNIQUES, SAMSUNG, SK HYNIX, SMIC, TOPPAN PHOTOMASKS, TOSHIBA, TSMC, VARIABLE-SHAPE BEAM, VSB
Industry leaders in EDA & foundry services collaborate with academia to explore future possibilities of CMOS/MEMS integration
Dresden, Germany – March 16, 2016 – Jointly sponsored by Cadence Design Systems, Coventor, X-FAB and Reutlingen University, a new MEMS Design Contest is being launched at DATE 2016. The objective of this contest is to encourage greater ingenuity with regard to the integration of MEMS devices and mixed-signal CMOS blocks. To kick off the contest, an informative session will be held in the Exhibition Theatre on Thursday, March 17, 2016 from 14:00 to 17:30 and is open to all DATE attendees free of charge. read more…
By R. Colin Johnson, EE Times
LAKE WALES Fla.—Simplfying and popularizing microelectromechanical system (MEMS) design is the goal of the MEMS Design Contest announced yesterday (March 16) at the conference titled Data Automation and Test in Europe (DATE 2016, March 15 to 17, Dresden, Germany). More specifically, the contest encourages chip designers to add MEMS blocks to a chip design, using tools designed for the purpose.
Sponsored by Cadence Design Systems, Coventor, X-FAB and Reutlingen University, the contest will feature a special process design kit (PDK) that the winners will use to fabricate their MEMS chip at X-Fab. If interested attend the DATE session Launch of the Worldwide MEMS Design Contest.
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