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Got Air Gaps?

By Ryan Patz, Applied Materials

NAND Flash memory has become the driver of semiconductor technology and the four primary manufacturers are pushing hard to continue scaling in order to preserve margins. Smartphone growth continues to increase demand and revenue close to $30 Billion is expected for 2014. 3D NAND is not quite ready for “prime time” so significant effort is required to resolve current 2D limitations to enable 1x nm devices. The main process integration challenges include patterning the very small features (often employing quadruple spacer patterning technology), fill issues due to aspect ratios >10 and cell to cell interference [1].
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Next-Gen MEMS Simulation Tool Makes Life Easier for ASIC Designers

By Francoise von Trapp
3D In-Depth, EDA Tools
http://www.3dincites.com/

MEMS-Electrostatic-Comb-Drive-500x250

I don’t usually write about MEMS. But every once in a while, when MEMS (stands for micro-electromechanical systems) touches anything to do with 3D integration, usually at the system-level, I might veer slightly out of my comfort zone to interview a MEMS supplier about their latest developments. I find it’s a good way to learn about the synergies and to cross-pollinate information. Today was one of those days. I interviewed Steve Breit, PhD, VP of Engineering, Coventor, supplier of design automation software for MEMS and semiconductor applications. Breit reminded me that through silicon via technology (TSV), which is critical for 3D IC, owes a debt to MEMS. He’s right about that. So I figure a nod to MEMS now and again on 3D InCites isn’t out of place.

Breit briefed me on the company’s latest version of its MEMS+ modeling environment for accelerated development of advanced MEMS devices and systems, and what the improvements mean for ASIC designers who need to integrate MEMS devices into their system design.
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Breakthrough MEMS Models for System and IC Designers

Gunar Lorenz, PhD
Director, System Level Simulation

We just rolled out MEMS+ 5.0 with lots of new capabilities for our users. I discussed some of the new features, support of scanning mirrors in particular, in a previous post. This time I would like to focus on the new capabilities for exporting reduced order models (ROMs) of MEMS devices that system engineers can place in their Simulink schematics and IC designers can place in their circuit schematics.

Before getting into the technical stuff, allow me to provide some motivation. To design the control and signal processing electronics that go around every MEMS device, system engineers usually work in Simulink while circuit designers work in schematic entry tools such as Cadence Virtuoso. There’s a MEMS block in their flow diagram or schematic with an underlying model that captures the coupled electromechanical behavior of the MEMS device. It’s common practice to “hand craft” the MEMS behavioral model, but hand crafted models have many shortcomings: they’re usually over simplified, capturing only one degree of freedom and omitting nonlinear effects. Furthermore, it’s difficult to keep hand crafted models in sync with evolving device designs. All of these shortcomings can be avoided by using ROMs exported from MEMS+ instead of hand-crafted models.
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Coventor Expands MEMS Modeling Offering With Latest Release of MEMS+® Tool Suite

MEMS+ 5.0 features expanded library of device structures; enhanced model export capability improves speed and visualization for MEMS + IC design

CARY, North Carolina – September 8, 2014 – Coventor®, Inc., the leading supplier of design automation software for micro-electromechanical systems (MEMS), today announced immediate availability of the latest version of its MEMS+® design solution for accelerating development of advanced MEMS devices and systems. MEMS+ 5.0 features an expanded modeling library to enable simulation of a greater variety of devices, with a particular focus on the unique challenges of micro-mirrors and piezo-electric devices. It also adds a new capability to create and export reduced-order models (ROMs) to the MATLAB® Simulink® environment from The MathWorks, Inc. to enable extremely fast and accurate non-linear simulations of MEMS-based systems. This supplements the existing capability to export ROMs in Verilog-A format for simulations of MEMS with electronics in widely used EDA simulators such as the Cadence® Spectre® circuit simulator.
The MEMS+ suite enables MEMS and IC designers to rapidly explore and optimize designs in parallel in the MathWorks MATLAB/Simulink and Cadence Virtuoso® environments. It is a key part of Coventor’s platform, which also includes the CoventorWare® and SEMulator3D® suites. The platform provides a complete solution for designing and verifying state-of-the-art accelerometers, gyroscopes, microphones, microprojectors and many other types of MEMS sensors and actuators.
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Lead Semiconductor Software Development Engineer – Villebon sur Yvette (91), France

We are seeking a dynamic, proactive software development engineer with a background in semiconductor technology or semiconductor software tools. In this key engineering position, you will lead the development of new software features related to our European research efforts in advanced CMOS (450mm/10nm/7nm). You will work closely with the Coventor semiconductor process technology team to understand the technical requirements of our partners, particularly metrology tool vendors and TCAD (Technology CAD) users. You will participate in the design and development of software interfaces to share our 3D structural models with other software tools.

This opening is a great opportunity for a strong coder with good communication skills. You will have the chance to work on a young, innovative product and to work closely with a collaborative, skilled team in both Europe and the USA. It is expected that responsibilities in this role will grow as Coventor’s European development team expands. Some travel is expected (less than 20%). You will report to the US-based Director of Semiconductor Software and R&D.

Responsibilities include:

  • Collaborate with our applications team to define requirements for new software features
  • Lead the development effort to design and implement new features in C++ and Python
  • Unit testing and bug fixing
  • Help troubleshoot customer problems
  • Provide input to and review documentation, tutorials, and user training materials

Required Qualifications:

  • PhD degree in computer science, electrical engineering, or a related field
  • 6 or more years of professional software development experience, preferably related to semiconductor equipment, metrology or TCAD
  • Expert-level coding skills in C++
  • Strong aptitude for object oriented design
  • Experience developing a 3D modeling software product, using either a 3D solid modeling kernel (ACIS, Parasolid, etc.), 3D mesh generation, or equivalent.
  • Ability to clearly communicate technical concepts
  • Must be able to read and understand technical articles and documentation written in English
  • Must have a valid EU passport

Desirable Qualifications:

  • Experience with semiconductor metrology software, particularly model-driven metrology
  • Experience with semiconductor TCAD modeling software
  • Knowledge of semiconductor process technology
  • Python coding skills

Salary, job title and responsibilities will be commensurate with experience. This opening is in Villebon sur Yvette (91), close to Paris. If you are interested in this opportunity and you are authorized to work in France, e-mail your resume in English to job1834@coventor.com

SEMulator3D: GlobalFoundries Process Variation Reduction

by Paul McLellan
SemiWiki

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At SEMICON last month, Rohit Pal of GlobalFoundries gave a presentation on their methodology for reducing process variation. It was titled Cpk Based Variation Reduction: 14nm FinFET Technology.

Capability indices such as Cpk is a commonly used technique to assess the variation maturity of a technology. It looks at a given parameter’s variability and compares it to 6 sigma. The higher the number the better, 1.33 should have the process yielding close to 100% (for that parameter) and 2 is the full 6 sigma. Using Cpk makes it easy to track metrics to assess variation improvement for a technology. They can also be used as a gating item for technology milestone achievement. However, it is not truly an absolute value, it is a function of the specification limits.

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