Coventor Blog

Advanced Lithography and Process Variation Modeling Using SEMulator3D


Click on image to view animation of modeling

By:   Jimmy Gu, Coventor Technical Staff

One of the top and probably toughest challenges that process integrators are facing today in a silicon fab is process variability. As a former process integrator working hard to ramp up the yield of 22nm FinFET technology, I saw it first-hand. Looking back, I wish I was equipped with the SEMulator3D virtual fabrication platform, which is designed to address this type of process variability challenge. With the recent release of SEMulator3D 5.1, its process variability toolbox has just received a powerful new addition: the ability to model line edge roughness (LER) and line width roughness (LWR) in lithography.

Why is LER and LWR so relevant in state-of-the-art process technology? The continued scaling of transistor and interconnect feature size, and the introduction of 3D structures such as FinFETs and 3D NAND, has brought significant challenges to process control of key structural variation sources such as LER and LWR. These structural variations are typically introduced during a lithography process and carried through subsequent complex process integration schemes. The final end-of-line LER and LWR on the wafer can become yield limiting factors, by increasing transistor threshold voltage variations leading to SRAM read/write fails, or by reducing BEOL process margins causing open/shorts in interconnects. As a result, much effort has been placed on designing robust integration schemes and implementing new process changes to ensure healthy LER/LWR. Therefore, the ability to incorporate realistic LER/LWR modeling in lithography will add an important dimension of process variability that is needed to facilitate a process integrator’s day to day process development work.

As an example, I have recently worked on a test case with the SEMulator3D virtual fabrication platform, to find out how LER and LWR are carried through in a typical BEOL SAQP integration scheme. The goal of this study was to shine some light onto a few interesting questions:

1) How does etch and deposition alter LER on line edges respectively in a SAQP flow?

2) What is the frequency response of etch and deposition effects on LER?

3) What process factors determine the final LWR of the trenches?

4) How can one reduce LER and LWR?

In this work, the initial LER was applied through lithography. Using a random line generation algorithm, noise of characteristic wavelengths and amplitudes were superimposed to form exposure edges with the expected LER. The LER and LWR after each process was measured using advanced virtual metrology.  By carefully analyzing the virtual experiment data that was similar to data that might be gathered from a real fab, we’ve discovered a number of interesting results.   These results will be disclosed in a 2016 SPIE Advanced Lithography poster entitled “Predicting LER and LWR in SAQP with 3D virtual fabrication” (Paper 9782-22 in the Advanced Etch Technology for Nanopatterning Session). Please come to this informative poster session.   I am excited to explain and discuss this work in greater detail !

In the latest release of SEMulator3D 5.1, LER/LWR is fully integrated into our lithography engine by applying random noises on lithography line edges. The noise is characterized by RMS amplitude and correlation length following Fourier Synthesis techniques. Random edge noise can be applied in addition to any other lithography variability parameters such as CD bias and mask shifts, capturing most of the variation sources associated with a lithography process. I believe that the new LER modeling capabilities in SEMulator3D will generate many valuable use cases, helping engineers tackle the toughest process variation challenges.

MEMS+ 6.0 takes on MEMS/IoT integration challenges

 Visualization of 3-axis MEMS gyro, courtesy of Murata Oy, simulated with MEMS+ model in MATLAB

Visualization of 3-axis MEMS gyro, courtesy of Murata Oy, simulated with MEMS+ model in MATLAB

We announced the release of the latest version of our MEMS+ design platform this week, MEMS+ 6.0. This release contains many new features and performance improvements that existing customers will appreciate as well as new capabilities that address key challenges of integrating MEMS with IoT devices. There’s far too much to talk about in one blog, so we will focus this one on why MEMS are critical to IoT and the key MEMS/IoT integration challenges MEMS+ 6.0 addresses. Subsequent blogs will expand on each of these challenges and our solutions.

First, let’s talk about the IoT, or Internet of Things. Unless you’ve been marooned on a remote island for a few years, you know that the IoT is the tech topic du jour, subject of much hype as well as growing reality. The IoT spans a wide range of technologies, including smart devices that interact with their environment, wireless technologies, internet infrastructure, big data, cloud infrastructure, software infrastructure, and software applications. It is widely acknowledged that low-cost sensors in general and MEMS in particular are a key enabler if not a defining characteristic of IoT.  A recent McKinsey report titled The Internet of Things: Mapping the Value Beyond the Hype states: “We define IoT as sensors and actuators connected by networks to computing systems. These systems can monitor or manage the health and actions of connected objects and machines. Connected sensors can also monitor the natural world, people, and animals.” The report goes on to say, under the topic of technology enablers: “Low-cost, low-power sensors are essential, and the price of MEMS (micro-electromechanical systems) sensors, which are used in smartphones, has dropped by 30 to 70 percent in the past five years.” The smart phones that most of us now keep with us 24/7 epitomize the first of many new IoT devices. They are packed with sensors, most notably MEMS motion sensors (accelerometers and gyroscopes) and MEMS microphones, and connect to the internet. Without MEMS, there would be no IoT or certainly less IoT.

For the now, say the next couple years, most IoT devices will be designed around available MEMS-based packaged parts with digital interfaces. The integration of the MEMS sensing elements with surrounding analog/mixed-signal (A/MS) electronics will be handled by the MEMS suppliers and the IoT designers only have to deal with sensor integration at the digital design and software/firmware levels. Looking ahead though, say three years and beyond, it’s a safe bet that market demands and competitive pressures will require IoT devices with lower cost, smaller size, lower power and higher performance. All those good things can only happen with a higher level of multi-technology integration at the package, wafer and die levels. There will be more MEMS devices on each die and more integration of MEMS and A/MS through wafer bonding. And there will be more integration of multiple technologies such as MEMS, A/MS, digital logic, memory and RF within a package through tried-and-true wire bonding and evolving through-silicon-via (TSV) technology. Developers of high-volume consumer IoT devices will lead the charge, but sooner or later the higher package-level integration demands will reach all market segments. For this increasing package-level integration to come to pass, IoT developers will require the sophisticated MEMS integration like the solutions that Coventor offers.

Here are the three key MEMS/IoT integration challenges that MEMS+ 6.0 addresses:

  • Provide a robust design flow for including MEMS in system designs in the MathWorks environment and circuit design in the Cadence environment;
  • Provide a platform for MEMS Process Design Kits (PDKs) to accelerate growth of the fabless/fab-lite business model for MEMS; and
  • Accurately predicting packaging effects on MEMS sensors (see my recent editorial in Chip Scale Review on this topic).

I’ll expand on each of these challenges and how MEMS+ 6.0 addresses them in future blogs.

VP of Business Development Blog

By Dinesh Bettadapur
July 2015

I was recently promoted to the Coventor executive management team as VP of Business Development assuming primary responsibility for driving business strategy and growth across the global semiconductor equipment market while also continuing to focus on driving market share growth across the Western US for the memory & logic IDMs as well as validation of the business potential for the fabless IC market.
read more…

SEMulator3D 5.0 – It’s ALMOST HERE!!!!

By David M. Fried

I said I’d follow up with another blog about new features and capabilities SEMulator3D 5.0… and I’m running out of time. The Gold release is less than a week away!!
In the last blog, I gave a general overview of the new release and I talked about the all new dopant-handling capabilities, so let’s just jump right into another topic…Visibility!
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Collaboration Brings Fast Analysis to Acoustic Resonator Design

By Mattan Kamon

After some lively conversations with the top researchers in MEMS acoustic resonators during the 2014 Sensors and Actuators Workshop (familiarly known to the MEMS community as “Hilton Head”) we were motivated to develop a simulation solution that would better serve these researchers as well as commercial designers. With the recent release of CoventorWare 10, we introduced a new fast analysis capability for acoustic resonators that is unique in the industry and I’m excited to blog about it here.
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Don’t miss new Cloud-Based 3D Design-Technology Checking (3D-DTC) demo at DAC!

DAC 2015 is in full swing in San Francisco this week, and Coventor is there again. But this year, we’re also doing a special joint demonstration with Silicon Cloud International. This demonstration combines the power of Coventor’s SEMulator3D Virtual Fabrication platform with broad parallel computing offered by Silicon Cloud to produce a whole new capability that we call “3D Design-Technology Checking” or 3D-DTC for short (not DRC!).
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SEMulator3D 5.0 – It’s COMING!!!

David M. Fried

This is my favorite part of the year at Coventor: We’re about to do another MAJOR release of SEMulator3D. Developers are sprinting to the finish line, customers are clamoring for the newest features. I’d like to start talking about the new features of SEMulator3D 5.0, but one blog certainly won’t cover it all. Let’s get started, and we’ll do this as many times as we need to get it all written down.
read more…

MEMS System Co-Design at DTIP

By Gerold Schröpfer

The 17th edition of the Symposium on Design, Test, Integration & Packaging of MEMS and MOEMS (DTIP 2015) took place this year in Montpellier, Southern France, on April 28-30. This conference brings together participants interested in MEMS fabrication with those interested in design tools and methods. While this annual event is always located in Southern Europe, it attracts attendees from both industry and academia from around the world.

It was my pleasure to chair a session titled Co-design for MEMS-based Smart Systems. In recent years, Coventor has made several crucial advancements, now embodied in MEMS+®, to bridge the gap between MEMS device design and system-level simulation. A number of MEMS+ users presented co-simulation results for systems that included inertial sensors, resonators, varactors and micromirrors. It was impressive and gratifying to see their achievements and hear their enthusiasm.

  • Guilherme Brondani Torri of imec presented the co-design of a MEMS-CMOS autonomous switched oscillator. He investigated how the dynamic response is affected by the operating point and environmental parameters. The co-simulation of MEMS and circuitry made it possible to identify important issues related to the stability of the proposed oscillator. [1]
  • Gaelle Lissorgues of ESSIE talked about a complete system design for an RF tunable agile filter. The parametric MEMS+ models for MEMS varactors and switches allowed optimizing the design with respect to manufacturing variations. Automated transfer of the MEMS+ model into Verilog-A allows for system-level simulation in ADS including RF performance estimation.[2]
  • Alessandro Sanginario of IIT Torino presented a MEMS+ based methodology for MEMS-IC-package co-design. The methodology takes into account the effects of thermally-induced stress on the package on inertial sensor transient behavior. He stated that, being an electronic designer, “it’s fantastic” to have a MEMS-package model in your familiar simulation language. [3, 4]
  • Fabio Cenni of ST Micro discussed a new extension to SystemC for MEMS system analysis, named SystemC-AMS/MDVP (Analog/Mixed Signal/Multi-Domain Virtual Prototyping) . This allows co-simulating not only MEMS with electronic hardware, but also with control software. The approach supports different levels of abstraction which allows balancing accuracy and simulation time. Fabio’s presentation was accompanied by a poster, written by Benoit Vernay of Coventor, demonstrating a prototype for automated extraction of a SystemC-AMS reduced-order models from MEMS+. [5, 6, 7]

Finally, my personal favorite was an invited presentation by Johannes Eisenmenger of Carl Zeiss. From a system-integrator point of view, he discussed the opportunities and challenges for EDA tools in developing optical systems. Optimizing such systems with suitable behavioral models is an essential step toward developing products for which new MEMS and other components need to be developed in parallel and their individual specifications depend on mutual interactions and environmental influences. One prominent example is the MEMS mirror matrix, FlexRay, employed in ASML’s 193nm UV lithography equipment for advanced CMOS. [8]

I want to warmly thank our customers for sharing their work with the MEMS system community.

MEMS-CMOS Autonomous Switched Oscillator presented by Guilherme Brondani Torr (© imec) [1]

MEMS-CMOS Autonomous Switched Oscillator presented by Guilherme Brondani Torr (© imec) [1]

Agile Filter assembly using MEMS switches and varactors presented by Gaelle Lissorgues [2]

Agile Filter assembly using MEMS switches and varactors presented by Gaelle Lissorgues [2]

MEMS-Package Co-Design presented by Alessandro Sanginario (© IIT, ST, Coventor) [3]

MEMS-Package Co-Design presented by Alessandro Sanginario (© IIT, ST, Coventor) [3]

Proceedings of International Conference on Design, Test, Integration and Packaging of MEMS and MOEMS (DTIP), Montpellier, France, 27-30 April 2015
[1] Guilherme BRONDANI TORRI (imec / KU Leuven – Belgium), Jan BIENSTMAN, Xavier ROTTENBERG, Harrie TILMANS (imec) ea, Co-Design of a MEMS-CMOS Autonomous Switched Oscillator
[2] Gaelle LISSORGUES (ESIEE Paris – France), Pierre NICOLE (THALES Systèmes Aéroportés – France), Julien PAGAZANI (ESIEE – France) ea, A RF tunable Agile Filter: from component to system design
[3] Alessandro SANGINARIO (Istituto Italiano di Tecnologia – Italy), Sarah ZERBINI (STMicroelectronics – Italy), ea, New design methodology for MEMS-electronic-package co-design and validation for inertial sensor systems
[4] Michelangelo GROSSO (ST-POLITO – Italy), Giuliana GANGEMI, Salvatore RINAUDO (STMicroelectronics – Italy) ea, Enabling Smart System Design with the SMAC Platform
[5] Olivier GUILLAUME, Fabio CENNI (STMicroelectronics – France) ea.,SystemC-AMS/MDVP-based modeling for the virtual prototyping of MEMS applications
[6] Fabio CENNI STMicroelectronics – France) ea, Generation of user-defined input stimuli for virtual prototyping of MEMS sensors applications
[7] Benoit VERNAY, Arnaud KRUST (Coventor – France), ea, SystemC-AMS Simulation of a Biaxial Accelerometer based on MEMS Model Order Reduction
[8] Johannes Eisenmenger, Opportunities and challenges of Electronic Design Automation of MEMS-ASIC Systems – A system integrator’s perspective (INVITED)