Coventor Blog

Pattern Dependence Process Modeling

By:   Joseph Ervin, Director – Semiconductor Process & Integration Engineering

First order process modeling can help tremendously with process setup and integration challenges that occur in a semiconductor fabrication flow, by visualizing process variation problems “virtually” prior to actual fabrication.  In some instances, a deeper level of complexity needs to be added to the process model to capture the effects of variation in the process.  Specific examples include pattern dependent processes and effects that can impact the flow and potentially the final device, including etch, deposition, CMP, and others.  Understanding these pattern dependent processes can be important in understanding variations, macro to scribe effects, within array effects, and even feature scale effects.  Through process simulation, unexpected results can be captured before expensive hardware, devices or wafers are manufactured or characterized.  Even during yield ramps, these factors can be important in helping to understand and minimize yield detractors.  SEMulator3D is a virtual fabrication platform that can incorporate these complex effects and provide users with a deep level of understanding of their process flows, using rich process-accurate models. read more…

Coventor Makes History (Museum)

Art piece with award

Organizers of the 53rd Design Automation Conference (DAC) hosted an art show to highlight the creativity and artistry that goes into much of the work in the electronics industry.  Coventor was honored with the grand prize for our 3D sculpture, which modeled 14nm FinFET Technology.

Here’s the background on how we came to make this piece.   Of course we used SEMulator3D to generate the data.   Normally this is rendered on a computer screen but for this we used a state-of-the-art 3D printer from Stratasys.   We’ve printed 3D models in the past, but we knew we’d need to go significantly beyond our prior experience to make a bold statement.   We were assisted in this effort by our friends at GrabCad, a digital manufacturing hub that helps designers and engineers build great products faster.

With SEMulator3D we created a large model of 14nm FinFET transistors, across a wide area of SRAM design, at high resolution, integrated from starting wafer through Metal 3, with some artistic cut-outs for visibility.   The resulting model was beautiful and reinforced all the key advanced capabilities of SEMulator3D, including MultiEtch, Visibility-Limited Deposition, Selective Epitaxy and many others.

Art Piece

Once the model was created we then exported it using the new standard voxel-data import-export format.  We worked with a team from GrabCad to print the piece in full color. They were able to parse our model input into their printing format.  The tricky part was that their ink-jet resolution is nearly 10x the resolution of the model data in the size we wanted to print, so with only three colors in the printer, we had to dither the ink to get the 27 colors needed for the final output.

Once printed – the piece was packaged and shipped to Austin where it was on display for three days at DAC.   The sculpture generated a great deal of buzz and excitement, which culminated at the awards ceremony on Wednesday.  All the pieces in the Art Show were judged in several categories such as:  best visualization, best silicon photo, most inspiring, most insightful and most artistic. Coventor won the GRAND PRIZE, which went to the piece that stood out in all categories.   As the winner, our 14nm FinFET 3D Sculpture will now be moved to the Computer History Museum in Mountain View, CA where it will be on display for one year.

David Fried accepting DAC 2016 Art Contest award

Congratulations to everyone who had a hand in the creation of this piece and to the organizers of DAC for hosting the Art Show, with particular thanks to our colleagues at GrabCad.  We’re happy to have been part of this and honored to now be part of the Computer History Museum.

IMEC Partner Technical Week Review

IMEC Partner Technical Week Review

By:   Aurélie Juncker, Semiconductor Process & Integration Engineer

a.Fully aligned Via with Cu recess approach - Gayle Murdoch, b. STT-RAM - Davide Crotti, c. N10 Supernova2 process - Matt Gallagher

a. Fully aligned Via with Cu recess approach – Gayle Murdoch, b. STT-RAM – Davide Crotti, c. N10 Supernova2 process – Matt Gallagher

In March 2016, Coventor was invited to the biannual Partner Technical Week (PTW) at IMEC in Leuven, Belgium. IMEC, a world-leading research group in nanotechnology, organizes their Partner Technical Week every 6 months to present scientific results to their partners. During this week, a number of specialists from IMEC’s many partner companies also discuss their progress in areas related to IMEC’s research. This event brings together a large number of engineers who are specialists in their domain, and provides an interesting forum to leverage the scientific knowledge gained by IMEC and its partners. read more…

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Introducing SEMulator3D Version 5.2


By: Daniel Sieger, Lead Engineer, SEMulator3D Geometry and Michael Hargrove, Semiconductor Process & Integration Engineer

The SEMulator3D software platform has once again been updated and improved with significantly more features, making it the industry leader in semiconductor virtual fabrication.  read more…

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The Future of MEMS Sensor Design and Manufacturing

By:  Stephen Breit, VP of Engineering

I recently gave an invited talk at the IEEE Inertial Sensors 2016 symposium that discussed the future of commodity MEMS inertial sensor design and manufacturing. Inertial sensors comprise one of the fastest growing and most successful segments of the MEMS market. read more…

Will directed self-assembly pattern 14nm DRAM?

By: Mattan Kamon, PhD., Distinguished Technologist, R&D, Coventor

Matt's March 2016 Blog Graphic

But first, more generally, will directed self-assembly (DSA) join Extreme Ultraviolet (EUV) Lithography and next generation multi-patterning techniques to pattern the next memory and logic technologies?  Appealing to the wisdom of crowds, the organizers of the 2015 1st International DSA symposium recently surveyed the attendees, and nearly 75% believed DSA would insert into high volume manufacturing within the next 5 years, and nearly 30% predicted insertion within the next 2 years.   What is gating insertion?  The crowd rated defectivity as the most critical issue facing DSA.  This fact adds weight to memory being the first to be patterned with DSA.  This is because, as Roel Gronheid from IMEC pointed out last month at the SPIE Advanced Lithography conference [1], memory chips can tolerate single failing cells through redundancy and so can could tolerate higher defectivity in patterning (roughly 1 defect/cm2 compared to 0.01 defect/cm2 for logic).  Defectivity rates for DSA aren’t there yet (according to public information), but are rapidly approaching [2], [3]. read more…

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Advanced Lithography and Process Variation Modeling Using SEMulator3D


Click on image to view animation of modeling

By:   Jimmy Gu, Coventor Technical Staff

One of the top and probably toughest challenges that process integrators are facing today in a silicon fab is process variability. As a former process integrator working hard to ramp up the yield of 22nm FinFET technology, I saw it first-hand. Looking back, I wish I was equipped with the SEMulator3D virtual fabrication platform, which is designed to address this type of process variability challenge. With the recent release of SEMulator3D 5.1, its process variability toolbox has just received a powerful new addition: the ability to model line edge roughness (LER) and line width roughness (LWR) in lithography. read more…

MEMS+ 6.0 takes on MEMS/IoT integration challenges

 Visualization of 3-axis MEMS gyro, courtesy of Murata Oy, simulated with MEMS+ model in MATLAB

Visualization of 3-axis MEMS gyro, courtesy of Murata Oy, simulated with MEMS+ model in MATLAB

We announced the release of the latest version of our MEMS+ design platform this week, MEMS+ 6.0. This release contains many new features and performance improvements that existing customers will appreciate as well as new capabilities that address key challenges of integrating MEMS with IoT devices. There’s far too much to talk about in one blog, so we will focus this one on why MEMS are critical to IoT and the key MEMS/IoT integration challenges MEMS+ 6.0 addresses. Subsequent blogs will expand on each of these challenges and our solutions. read more…