Coventor Blog

Delivering the Next 5 Years of Semiconductor Technology

New, advanced semiconductor processing and architectural technologies take years to perfect and put into production. In the meantime, semiconductor customers continue to demand faster, smaller and higher functioning devices. Semiconductor manufacturers need to decide whether (and when) to jump to the next generation of devices and production technologies, weighing the risk and benefit of bringing the next processing and architecture technologies to market.

A recent example of this type of risk analysis can be found in the gradual plans by foundries to adopt EUV technology. EUV technologies will reduce current requirements for multi patterning and (eventually) improve yields. However, EUV technology has many technological hurdles, including mask defects, CD uniformity, and production rate and yield issues. Billions of dollars have been invested in EUV development, yet no foundry is currently using the technology in production.

Could we extend existing technology concepts to deliver the next generations of semiconductor scaling, and avoid or defer the risk of jumping to next generation device and production technologies? Or, does the industry need paradigm-shifting technologies to reach these goals? Is there a way that we squeeze additional angstroms out of existing process and technology elements? Can we use variation reduction and process control to create the next few generations of semiconductor scaling? Or, do we simply need entirely new processes and architectures to reach these difficult goals?

There might be an entire node of scaling available from variation reduction, with numerous opportunities for variation reduction in advanced technology development. Our ability to detect, measure and characterize variability issues will be critical in variation reduction, along with process optimization and co-optimization strategies and challenges. Process controls are a key factor in being able to reduce process variability and to scale effectively.

If you are interested in exploring this topic further, we invite you to attend a complimentary seminar sponsored by Coventor in San Francisco on December 5, 2017, entitled “Everything is Under Control:  Delivering the Next 5 Years of Semiconductor Technology”. The seminar will be moderated by Ed Sperling, Editor in Chief of Semiconductor Engineering. Leading semiconductor industry panelists will discuss alternative methods to solve fundamental problems of technology scaling, and review techniques and strategies that might extend the lifetime of the latest technologies and propel us into the future. They will explore the latest advances in semiconductor architectures, patterning, metrology, advanced process control, co-optimization and integration. If you are unable to attend the seminar, keep your eye on future issues of Semiconductor Magazine to view a summary of the discussion.

To pre-register for the complimentary panel discussion, click here.

Reducing BEOL Parasitic Capacitance using Air Gaps

By: Michael Hargrove, SP&I Engineer

Reducing back-end-of-line (BEOL) interconnect parasitic capacitance remains a focus for advanced technology node development. Porous low-k dielectric materials have been used to achieve reduced capacitance, however, these materials remain fragile and prone to reliability concerns. More recently, air gap has been successfully incorporated into 14nm technology [1], and numerous schemes have been proposed to create the air gap [2-3].  There are many challenges to integrate air gap in BEOL such as process margin for un-landed vias and overall increased process complexity. In this paper, we introduce virtual fabrication (SEMulator3D®) as a means to study air gap process integration optimization and resulting interconnect capacitance reduction. Initial calibration to published air gap data is demonstrated. read more…

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Using Advanced Statistical Analysis to improve FinFET transistor performance

By: Jimmy Gu, SP&I Staff Engineer

Trial and error wafer fabrication is commonly used to study the effect of process changes in the development of FinFET and other advanced semiconductor technologies.  Due to the interaction of upstream unit process parameters (such as deposition conformality, etch anisotropy, selectivity) during actual fabrication, variations based upon process changes can be highly complex. Process simulators that mimic fab unit processes can now be used to model these complex interactions.  They can also help process engineers identify important process and/or design parameters that drive certain critical targets such as CDs, yield limiting spacing, 3D design rule violations, resistance/capacitance, and other process and design issues.   The number of possible parameters that affect device performance and yield can be quite large, so statistical analysis can provide useful insight and help identify critical performance parameters.  Coventor’s SEMulator3D virtual fabrication (or process simulation) platform contains an analytics module for conducting virtual design-of-experiments and statistical analysis. I would like to use an example of a 14nm FinFET process flow in SEMulator3D to identify important process parameters that drive fin top CD, which is a key metric for transistor performance.

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Silicon Photonics: Solving Process Variation and Manufacturing Challenges

By: Sandy Wen, Principal Engineer

As silicon photonics manufacturing gains momentum with additional foundry and 300mm offerings, process variation issues are coming to light. Variability in silicon processing affects the waveguide shape and can result in deviation in effective indices, propagation loss, and coupling efficiency from the intended design. In this article, we will highlight process variation issues that can occur in silicon photonics manufacturing and discuss techniques to mitigate these effects.

Figure 1. Example test photonic IC, with common elements such as waveguides, grating coupler, MZI, photodetector and fill pattern.

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Are Good Engineers Born or Bred?

By Steve Breit, V.P. Engineering

I’ve been doing a lot of interviewing as we grow our engineering team. I often say that hiring is the most important part of my job and also the hardest part. Like any sensible technology company, Coventor wants to hire the best engineers we can find. Good engineers love engineering. They love to build, to create, to innovate, to solve problems. Good engineers are methodical and persistent, but also bring engineering judgment and intuition that helps them arrive at solutions efficiently. Good engineers can’t help doing engineering – it’s who they are. Over the years, I’ve observed that good engineers are way more productive than mediocre engineers. The difference in productivity can be astounding, in excess of 2 or 3X for the best engineers. The trick, at least during the hiring process, is to discern which candidates are the good engineers. You can’t just look at academic degrees, skills claimed, or work experience to tell the difference. read more…

The Future of MEMS Design: Making MEMS Design More Like CMOS Design

By: Christine Dufour, MEMS PDK Program Manager

MEMS-based component suppliers want to rapidly ramp their designs into high-volume production.  This demand is driving MEMS suppliers to focus on ways to more efficiently re-use established process steps, stacks or technology platforms. To meet this need, we see the emergence of standard MEMS technology and design platforms similar to those used in CMOS design.

The semiconductor industry and EDA vendors have established integrated design environments based on PDKs (Process Design Kits), standard cell libraries, memory architectures, and IP, to give easy access to the technology for IC designers and increase chances of first-pass successful silicon. Coventor’s vision is that the MEMS eco system and MEMS EDA software vendors should play a similar role in accelerating MEMS product development. read more…

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3D Model-Based Process Control for the Future of Smart Manufacturing

David Fried’s, CTO of Coventor, gave a presentation entitled “3D Model-Based Process Control for the Future of Smart Manufacturing” at SEMICON West 2017.

Listen to this presentation to gain an understanding of high-speed 3D process modeling and how model-based process control can be used to improve process yield of advanced semiconductor technologies.

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CMOS Image Sensors (CIS): Past, Present & Future

By: Sofiane Guissi, Semiconductor Process & Integration Engineer, Coventor

Over the last decade, CMOS Image Sensor (CIS) technology has made impressive progress. Image sensor performance has dramatically improved over the years, and CIS technology has enjoyed great commercial success since the introduction of mobile phones using on-board cameras. Many people, including scientists and marketing specialists, predicted 15 years earlier that CMOS image sensors were going to completely displace CCD imaging devices, in the same way that CCD devices displaced video capture tubes during the mid-1980’s. Although CMOS has a strong position in imaging today, it has not totally displaced CCD devices. On the other hand, the drive into CMOS technology has drastically increased the overall imaging market. CMOS image sensors have not only created new product applications, but have also boosted the performance of CCD imaging devices as well. In this paper, we describe the state-of-the-art in CMOS image sensor technology and discuss future perspectives.

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