Coventor Blog

Are MEMS bolometers the next big thing?

By Steve Breit, Vice President Engineering

I often feel that Coventor is in the crow’s nest for spotting trends in the MEMS industry because our customers use design and simulation software early in the product development cycle to evaluate and optimize new concepts. Through evaluation and support requests from our worldwide customer base, we get some visibility on the types of MEMS our customers are working on. We’re obligated, of course, to keep the details of customer requests confidential. But, when multiple customers start asking questions about a particular type of MEMS that previously hasn’t seen much activity, we begin to suspect a new trend is developing. Such is the case for MEMS bolometers, or microbolometers. read more…

SEMulator3D 2014: Why this is big news

by David M. Fried

We’re right on the cusp of the SEMulator3D 2014 release. This has been a big release in the making, and I know I’m not alone in my excitement as we approach release day. You can read the press release and get an updated data sheet, but I wanted to take the opportunity to give you my personal engineer-to-engineer perspective on why this is so exciting to anyone doing advanced process development. read more…

Some Thoughts on 3D Integration and How to Better Understand its Complexity

As semiconductor technology scales into the 20nm node and beyond, the process complexity, electrical performance and circuit density tradeoff becomes extremely difficult to optimize. As the demand for increased density, lower power, and higher bandwidth accelerates, the motivation for 3D integration becomes more attractive. With the advent of 3D integration comes the promise of “beyond Moore’s law” integration by stacking chip-on-chip and connecting them with through-silicon-vias (TSVs). Numerous definitions of 3D integration exist, for example multi-die packages (also known as system-in-package, or SiP) in which multiple die are mounted on a common substrate that connects them, package-in-package (PiP) where a number of SiPs are mounted in a larger SiP, and package-on-package (PoP) where one SiP is mounted on top of another SiP. All of these approaches offer some degree of density advantage, however, the ultimate objective of 3D integration is the multiple stacking of silicon levels on top of one another, each of which contain subsequent levels of circuitry, all connected with TSVs. This approach to 3D integration has been demonstrated by CEA-Leti and reported in IEEE Spectrum (see Figure 1 below). read more…

3D printed model of FinFET attracts attention at SPIE Conference

photo 1[1]

3D printing has become all the rage in many areas, from home hobbyists to high-end industrial applications. The convenience, flexibility, functionality and decreasing price for printing things in 3D makes it an appealing tool for a wide range of purposes. So we thought we’d put it to use for demonstrating how virtual fabrication can help engineers understand the technical nuances of advanced process technologies – as well as show off a cool feature of our SEMulator3D tool. read more…

IEEE Conference Highlights the MEMS Opportunity

The recent IEEE Conference on MEMS, held in San Francisco, was one of the better gatherings of its sort, partly due to the location and its proximity to so many participants in the MEMS community, and partly because MEMS is at a real turning point and it is an industry primed for great innovation and advances that can touch all aspects of our lives.

The conference is literally a ‘who’s who’ of the MEMS industry, and not surprisingly there are excellent technical talks on the most important and popular MEMS-related topics such as gyros and accelerometers, optical MEMS, resonators and RF MEMS, energy harvesting and fluidic micro-devices, and biomedical micro-devices. There are tracks covering the complete range of MEMS development – from design, to materials and process characterization, through to fabrication. And there are some pretty advanced, even exotic, topics presented, particularly in the area of health and medical applications.
read more…

This is not your Father’s TCAD

By David Fried

SRAM_M3_CutawayWhen I started my semiconductor career, in the midst of quarter-micron CMOS, the work of technology development was very different. We basically knew how to fabricate transistors and interconnects. The structures were pretty well defined, and each generation we embarked on scaling a few key parameters and then resetting the device.

This is not to say that there was a lack of innovation. The industry was undergoing the conversion to copper in the BEOL and some of us to SOI substrates, which represented significant integration, materials and reliability challenges.

But, other than those “big ticket” changes, the processes and integration were stable enough that a large portion of the development effort fell on device engineering. The biggest degrees of process freedom existed in implants and anneals. We spent huge time and resources running and analyzing implant split experiments, clawing out that last 2-3% of drive current and dialing down that last 10-20nA of leakage. As such, TCAD device simulations were absolutely essential. Most process variations were small enough relative to target dimensions to be largely ignored, so TCAD results could directly guide implant and anneal process decisions. read more…