Coventor Blog

Comparing MEMS and the RMS Titanic: Some Thoughts from the IEEE MEMS 2018 Conference

By: Chris Welham, Sr. Manager, MEMS Applications Engineering

Conference dinner view of the life-size outlines of the Titanic and Olympic main deck’s, illuminated by blue light

How are MEMS and Large Ships Alike?

MEMS 2018 was held in Belfast, Northern Ireland this year, on the site where the RMS Titanic was built. On exhibit was the SS Nomadic, a tender used to transfer mail and passengers to the RMS Titanic and her sister ship RMS Olympic. Passing by the SS Nomadic on the way to the conference dinner, I noticed the riveted plates from which the tender was built. These riveted plates reminded me of the finite element plate models used in the MEMS+ module of CoventorMP, which can also be joined to other elements using “connectors” or “nodes” rather than rivets.

I wondered what other components in MEMS+ existed in the Titanic? For sure, perforated plates, or baffles. Many MEMS devices use perforated plates, either to aid the release etch in fabrication or for reasons of operation. Release etch, and the effects of pattern dependence, are key fabrication processes modeled in our virtual fabrication tool, SEMulator3D. A condenser microphone, which can be modeled using MEMS+, has at least one perforated back plate. Steel beams, too? Certainly, MEMS+ has Timoshenko Beam models, the underlying theory of which was first developed by Stephen Timoshenko just before the Titanic sank. Further comparison was harder. Comb capacitors? Well only as tuning condensers in the on-board Marconi Wireless Set, as it was then known. Fluid dampers? Perhaps in the engine supports of the SS Nomadic to reduce vibration.

What happened at the IEEE MEMS Conference?

Back to the conference, there was a wide range of interesting presentations and posters. Topics covered ranged from inertial sensors, actuators, acoustics, resonators and RF MEMS (all areas where we specialize), through to material science and microfluidics. It was good to see our tools being used to simulate a range of MEMS devices. We also had the opportunity to discuss emerging research in the area of MEMS simulation, which is always important for us to follow to ensure that our tools retain their leading edge capabilities.

What’s New with CoventorMP?

Incidentally, there are exciting new features for microphone design in the upcoming CoventorMP release, due out this Spring. We’re also expanding our capabilities for modeling suspension beams as well as lots of other new features. More to follow on these exciting enhancements as we get closer to the release date!

Future Outlook: The Advantages of Fully Depleted Silicon on Insulator (FD-SOI) Technology

By: Michael Hargrove, SP&I Engineer

If my memory serves me well, it was at the 1989 Device Research Conference where the potential merits of SOI (Silicon on Insulator) technology were discussed in a heated evening panel discussion. At that panel discussion, there were many advocates for SOI, as well as many naysayers. I didn’t really think more about SOI technology until the mid-nineties, when I was sitting in a meeting where the first SOI device data was being presented in the hallowed halls of IBM. The data was incredibly scattered and my thinking was “this technology is going nowhere!” The purported performance advantage was stated to be ~35%, simply due to the capacitance reduction (no longer did the bottom junction capacitance play a role) and the speed advantages of stacked devices in a NAND circuit. It all sounded great, but in the mid-nineties, the data simply didn’t support it. Nonetheless, the SOI advocates pursued their beloved technology, and the rest is history. SOI technology has been part of IBM’s main stream high-performance technology base through the 14nm node, including FinFETs on SOI. read more…

What the Experts Think: Delivering the Next 5 Years of Semiconductor Technology

Coventor recently sponsored an expert panel discussion at IEDM 2017 to discuss how we might advance the semiconductor industry into the next generation of technology.  The panel discussed alternative methods to solve fundamental problems of technology scaling, using advances in semiconductor architectures, patterning, metrology, advanced process control, variation reduction, co-optimization and new integration schemes.  Our panel included Rick Gottscho, CTO of Lam Research; Mark Dougherty, vice president of advanced module engineering at GlobalFoundries; David Shortt, technical fellow at KLA-Tencor; Gary Zhang, vice president of computational lithography products at ASML; and Shay Wolfling, CTO of Nova Measuring Instruments.

The Next 5 Years of Semiconductor Technology

L-R: Ed Sperling (moderator), Shay Wolfling, Rick Gottscho, Mark Dougherty, Gary Zhang, David Shortt

Here are a few expert predictions for the next 5 years of semiconductor technology that came out of the discussion:

FinFETs will get extended to at least to 5nm, and possibly 3nm

Rick Gottscho of Lam Research felt that FinFETs will get extended to at least 5nm, and possibly 3nm.    Shay Wolfing of Nova Measuring Instruments predicted that nanosheet technology could be used after FinFET extensions would not scale further.

EUV will be used at new nodes, followed by High NA Lithography

Gary Zhang of ASML stated that EUV will drive lithography at new nodes, with high-NA as an extension to EUV on the technology roadmap. Gary felt that managing the complexity and the cost of these new lithography techniques will be challenging, but feasible.

Materials and basic structures may diverge by supplier, at 7 nm and beyond

Mark Dougherty of GlobalFoundries noted that suppliers may not align at the end of the day on the same materials and basic structures to scale semiconductor technology. It’s possible that there might be some divergence, such as in back-end-of-line metallurgy.

Metrology can meet future technical challenges, but inspection and measurement costs may rise

Gary Zhang confirmed that 3D measurements below an angstrom are now possible, and that we have metrology solutions available for the near future.   David Shortt of KLA-Tencor asserted that end-to-end cycle time and cost are increasing for inspection and metrology, and that these trends may continue unless technical risk reduction is started early in the development process.

3D NAND technology will continue scaling beyond the existing 48 layer structures

Rick Gottscho stated that he sees a path over the next 10 years to scale 3D NAND manufacturing technology, up to 256 layers.   Rick had some concerns over film stress and challenging etch requirements in meeting this scaling projection.

If you are interested in reading more about this panel, you can find the first part of the panel transcript at Semiconductor Engineering.   Future articles in Semiconductor Engineering will highlight the remainder of the panel discussion, including the expert’s views on the role of advanced process control, variation reduction, co-optimization and new integration schemes in delivering the next 5 years of semiconductor technology.

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Delivering the Next 5 Years of Semiconductor Technology

New, advanced semiconductor processing and architectural technologies take years to perfect and put into production. In the meantime, semiconductor customers continue to demand faster, smaller and higher functioning devices. Semiconductor manufacturers need to decide whether (and when) to jump to the next generation of devices and production technologies, weighing the risk and benefit of bringing the next processing and architecture technologies to market.

A recent example of this type of risk analysis can be found in the gradual plans by foundries to adopt EUV technology. EUV technologies will reduce current requirements for multi patterning and (eventually) improve yields. However, EUV technology has many technological hurdles, including mask defects, CD uniformity, and production rate and yield issues. Billions of dollars have been invested in EUV development, yet no foundry is currently using the technology in production.

Could we extend existing technology concepts to deliver the next generations of semiconductor scaling, and avoid or defer the risk of jumping to next generation device and production technologies? Or, does the industry need paradigm-shifting technologies to reach these goals? Is there a way that we squeeze additional angstroms out of existing process and technology elements? Can we use variation reduction and process control to create the next few generations of semiconductor scaling? Or, do we simply need entirely new processes and architectures to reach these difficult goals?

There might be an entire node of scaling available from variation reduction, with numerous opportunities for variation reduction in advanced technology development. Our ability to detect, measure and characterize variability issues will be critical in variation reduction, along with process optimization and co-optimization strategies and challenges. Process controls are a key factor in being able to reduce process variability and to scale effectively.

If you are interested in exploring this topic further, we invite you to attend a complimentary seminar sponsored by Coventor in San Francisco on December 5, 2017, entitled “Everything is Under Control:  Delivering the Next 5 Years of Semiconductor Technology”. The seminar will be moderated by Ed Sperling, Editor in Chief of Semiconductor Engineering. Leading semiconductor industry panelists will discuss alternative methods to solve fundamental problems of technology scaling, and review techniques and strategies that might extend the lifetime of the latest technologies and propel us into the future. They will explore the latest advances in semiconductor architectures, patterning, metrology, advanced process control, co-optimization and integration. If you are unable to attend the seminar, keep your eye on future issues of Semiconductor Engineering to view a summary of the discussion.

To pre-register for the complimentary panel discussion, click here.

Reducing BEOL Parasitic Capacitance using Air Gaps

By: Michael Hargrove, SP&I Engineer

Reducing back-end-of-line (BEOL) interconnect parasitic capacitance remains a focus for advanced technology node development. Porous low-k dielectric materials have been used to achieve reduced capacitance, however, these materials remain fragile and prone to reliability concerns. More recently, air gap has been successfully incorporated into 14nm technology [1], and numerous schemes have been proposed to create the air gap [2-3].  There are many challenges to integrate air gap in BEOL such as process margin for un-landed vias and overall increased process complexity. In this paper, we introduce virtual fabrication (SEMulator3D®) as a means to study air gap process integration optimization and resulting interconnect capacitance reduction. Initial calibration to published air gap data is demonstrated. read more…

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Using Advanced Statistical Analysis to improve FinFET transistor performance

By: Jimmy Gu, SP&I Staff Engineer

Trial and error wafer fabrication is commonly used to study the effect of process changes in the development of FinFET and other advanced semiconductor technologies.  Due to the interaction of upstream unit process parameters (such as deposition conformality, etch anisotropy, selectivity) during actual fabrication, variations based upon process changes can be highly complex. Process simulators that mimic fab unit processes can now be used to model these complex interactions.  They can also help process engineers identify important process and/or design parameters that drive certain critical targets such as CDs, yield limiting spacing, 3D design rule violations, resistance/capacitance, and other process and design issues.   The number of possible parameters that affect device performance and yield can be quite large, so statistical analysis can provide useful insight and help identify critical performance parameters.  Coventor’s SEMulator3D virtual fabrication (or process simulation) platform contains an analytics module for conducting virtual design-of-experiments and statistical analysis. I would like to use an example of a 14nm FinFET process flow in SEMulator3D to identify important process parameters that drive fin top CD, which is a key metric for transistor performance.

read more…

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Silicon Photonics: Solving Process Variation and Manufacturing Challenges

By: Sandy Wen, Principal Engineer

As silicon photonics manufacturing gains momentum with additional foundry and 300mm offerings, process variation issues are coming to light. Variability in silicon processing affects the waveguide shape and can result in deviation in effective indices, propagation loss, and coupling efficiency from the intended design. In this article, we will highlight process variation issues that can occur in silicon photonics manufacturing and discuss techniques to mitigate these effects.

Figure 1. Example test photonic IC, with common elements such as waveguides, grating coupler, MZI, photodetector and fill pattern.

read more…

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Are Good Engineers Born or Bred?

By Steve Breit, V.P. Engineering

I’ve been doing a lot of interviewing as we grow our engineering team. I often say that hiring is the most important part of my job and also the hardest part. Like any sensible technology company, Coventor wants to hire the best engineers we can find. Good engineers love engineering. They love to build, to create, to innovate, to solve problems. Good engineers are methodical and persistent, but also bring engineering judgment and intuition that helps them arrive at solutions efficiently. Good engineers can’t help doing engineering – it’s who they are. Over the years, I’ve observed that good engineers are way more productive than mediocre engineers. The difference in productivity can be astounding, in excess of 2 or 3X for the best engineers. The trick, at least during the hiring process, is to discern which candidates are the good engineers. You can’t just look at academic degrees, skills claimed, or work experience to tell the difference. read more…