Coventor Blog

Got Air Gaps?

By Ryan Patz, Applied Materials

NAND Flash memory has become the driver of semiconductor technology and the four primary manufacturers are pushing hard to continue scaling in order to preserve margins. Smartphone growth continues to increase demand and revenue close to $30 Billion is expected for 2014. 3D NAND is not quite ready for “prime time” so significant effort is required to resolve current 2D limitations to enable 1x nm devices. The main process integration challenges include patterning the very small features (often employing quadruple spacer patterning technology), fill issues due to aspect ratios >10 and cell to cell interference [1].
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Breakthrough MEMS Models for System and IC Designers

Gunar Lorenz, PhD
Director, System Level Simulation

We just rolled out MEMS+ 5.0 with lots of new capabilities for our users. I discussed some of the new features, support of scanning mirrors in particular, in a previous post. This time I would like to focus on the new capabilities for exporting reduced order models (ROMs) of MEMS devices that system engineers can place in their Simulink schematics and IC designers can place in their circuit schematics.

Before getting into the technical stuff, allow me to provide some motivation. To design the control and signal processing electronics that go around every MEMS device, system engineers usually work in Simulink while circuit designers work in schematic entry tools such as Cadence Virtuoso. There’s a MEMS block in their flow diagram or schematic with an underlying model that captures the coupled electromechanical behavior of the MEMS device. It’s common practice to “hand craft” the MEMS behavioral model, but hand crafted models have many shortcomings: they’re usually over simplified, capturing only one degree of freedom and omitting nonlinear effects. Furthermore, it’s difficult to keep hand crafted models in sync with evolving device designs. All of these shortcomings can be avoided by using ROMs exported from MEMS+ instead of hand-crafted models.
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The Unsung Heroes of CoventorWare

By Steve Breit, Vice President Engineering

The CoventorWare 2014 release has been announced and is now available to customers. I presided over the first release of CoventorWare in 2001 and eight major releases since then with numerous updates in between. With each release, we added new capabilities, and capacity, speed, and accuracy improvements to address the ever more demanding requirements of our users. The new capabilities and performance improvements in each release are easy to talk about and receive all the glory. In this respect, CoventorWare 2014 is no different: the highlights are covered in our press release and a What’s New page elsewhere on our site; I won’t repeat them here. Instead, I want to talk about the steady improvements in the usability, robustness and quality of the software and the documentation. These improvements aren’t as glamorous as the shiny new stuff, but I believe they really matter to users. Our quality assurance team and our documentation team deserve a lot of credit for these improvements. They’re the unsung heroes of CoventorWare.
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Semicon West attracts the entire value chain to address 3D chip manufacturing challenges

Semicon West is one of the iconic conferences in the semiconductor industry and annually attracts the key movers and shakers who are involved with how we are going to keep Moore’s Law moving forward, among other things. It’s known rightfully so, as a ‘big iron’ show with the top manufacturing equipment companies showing off their newest machines for the major steps in the manufacture of semiconductors – wafer processing, assembly packaging and test.

It’s not all about the equipment of course, or even just manufacturing. The show has done a good job of expanding to include a wider ecosystem of companies, products and topics that impact chip design as well. So while the majority of attendees come from companies that produce chips – foundries and IDMs – as well as the supporting production services, Semicon visitors also include the fabless companies who really aren’t in the market for manufacturing equipment. read more…

Mid summer release of SEMulator3D adds more accuracy for deposition & CMP

By David M. Fried

Today we officially released SEMulator3D 2014.100. Typically, I wouldn’t be so excited about a “point release”, but this is clearly the biggest interim software release in recent SEMulator3D memory. We’ve added significant capability to an already industry-leading virtual fabrication platform. Many of the features of recent SEMulator3D releases have been focused on Etch enhancements. To complement these enhancements, we’ve stepped up the predictive accuracy of several other process models in SEMulator3D 2014.100, including Deposition and CMP.

The highlight of this release is a new Visibility-Limited Deposition model. This model dramatically improves the predictive accuracy for directional depositions, like Physical Vapor Deposition (PVD) and other plasma enhanced deposition processes. As with other process models in SEMulator3D, we’ve made this process simple to implement and calibrate using a reduced set of process parameters. The key features of this Visibility-Limited Deposition model are the “Source Sigma”, reflecting the directional distribution of the process, and the “Isotropic Ratio”, reflecting the non-visibility-limited component of the deposition process. This model enables a large variety of processes, with a wide range of results.
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Linking Virtual Wafer Fabrication Modeling with Device-level TCAD Simulation

By Mike Hargrove

Most process/device simulation tools are TCAD-based. By this, I mean they share a common platform which connects the process simulator to the device simulator, usually using the same mesh structure. Most all of these TCAD tools are finite-element based, and the 3D final mesh structure is tetrahedral in nature. The mesh structure contains many nodes which define solution points for the numerous complex set of equations required to create the physical structure, in most cases a transistor, and solve for the electrical characteristics of the device. One of the drawbacks of TCAD is the computational time required to arrive at a solution – both process model solution and device electrical solution. A larger modeled area (e.g. multiple transistors and/or an SRAM cell) usually means longer simulation time.

Coventor’s virtual wafer fabrication approach addresses this challenge. Our process modeling platform combines with the statistical device TCAD suite of tools from Gold Standard Simulations, LTD. (GSS) to produce SRAM device-level simulation capability capturing real process-induced statistical variation. The ultimate objective of statistical device modeling is to capture the intrinsic variation of physically relevant process parameters. The combination of Coventor SEMulator3D process modeling capability and GSS statistical TCAD simulator GARAND fulfills this objective.
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