Coventor Blog

What drives SADP BEOL variability?

By: Michael Hargrove, Semiconductor Process & Integration Engineer

Until EUV lithography becomes a reality, multiple patterning technologies such as triple litho-etch (LELELE), self-aligned double patterning (SADP), and self-aligned quadruple patterning (SAQP) are being used to meet the stringent patterning demands of advanced back-end-of-line (BEOL) technologies.  For the 7nm technology node, patterning requirements include a metal pitch of 40nm or less. This narrow pitch requirement forces the use of spacer based pitch multiplication techniques. Unfortunately, these techniques have high process/lithography variability, which can severely impact RC and overall device performance.

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Photoresist shape in 3D: Understanding how small variations in photoresist shape significantly impact multi-patterning yield

By: Mustafa B. Akbulut, Ph.D., Team Lead, Quality Assurance, Semiconductor Solutions

Things were easy for integrators when the pattern they had on the mask ended up being the pattern they wanted on the chip. Multi-patterning schemes such as Self-Aligned Double Patterning (SADP) and Self-Aligned Quadruple Patterning (SAQP) have changed that dramatically. Now, what you have on the mask determines only a part of what you will get at the end. read more…

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MEMS Microphones – A Bright Spot among Commoditized Consumer Sensors

By: Jun Yan, Ph.D., MEMS Technical Director

MEMS Microphone picture

Source: InfineonTechnologies, AG, “The Infineon Silicon MEMS Microphone”, DOI:10.5162/sensor2013/A4.3

MEMS microphones have emerged as a bright spot among consumer sensors, which in general are going through a rapid commoditization and profit-squeezing trend.

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Semiconductor Process Development: Finding a Faster Way to Profitability

By: Katherine Gambino, Strategic Accounts Manager

Intel Fab

Building a chip fabrication facility requires billions of dollars in investment for land, buildings, processing equipment, chemical and hazardous material safety, not to mention the deployment of hundreds of highly experienced process engineering and manufacturing personnel. Bringing up an advanced semiconductor process in any fab, new or established, is a several-hundred-million dollar effort, typically requiring two or more years of experimentation with process equipment and process recipes, led by engineers with years of process integration and chip manufacturing expertise.

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The Value of Integrating Process Models with TCAD Simulation (and some tips on how to do it)

By: Shi Hao (Jacky) Huang, PhD, Semiconductor Process & Integration Engineer

Coventor January 2017 Blog Graphic

Coventor January 2017 Blog Graphic 2

 

 

 

 

Nowadays, novel semiconductor technologies have brought complex process flows to the fab.   These process flows are needed to support the manufacturing of advanced 3D semiconductor structures. It can be helpful to model process flows, and their effect on a novel device, prior to physical fabrication.

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BEOL Barricades: Navigating Future Yield, Reliability and Cost Challenges

By: David Fried, Ph.D., Chief Technology Officer, Semiconductor

Figure 1. M2-V1 process flow after (a) M2-L1 lithography, (b) M2-L2 litho, (c) V1 partial etch, (d) BLok open and (e) CuBS.

Coventor recently assembled an expert panel at IEDM 2016, to discuss changes to BEOL process technology that would be needed to continue dimensional scaling to 7 nm and lower. We asked our panelists questions such as: read more…

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Bringing Advanced Semiconductor Manufacturing Technologies to Higher Education

By: Jimmy Gu, Ph.D., Semiconductor Process & Integration Engineer, Coventor

Campus image for November 2016 blog

Universities and other institutions of higher learning play a key role in developing our next generation of semiconductor technologies. Along with the theory of semiconductor technology, our next generation of scientists and engineers must learn about the practical methods used to design and manufacture the latest generation of semiconductor products. read more…

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Achieving the Vision of Silicon Photonics Processing

By: Sandy Wen, MSEE, Semiconductor Process and Integration Engineer, Coventor

Silicon Photonics Test Die

Silicon Photonics Test Die

With the increasing need for faster data transfer rates, the transition from electrical to optical signaling in data processing is inevitable.   Copper cabling cannot keep up with the upcoming data center bandwidth requirements, for applications such as multimedia streaming and high performance computing.  One technology that could enable true optical communication is silicon photonics. read more…

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