Coventor Blog

Design Process Technology Co-Optimization for Manufacturability

By:   Dalong Zhao – Semiconductor Process & Integration Engineering

Yield and cost have always been critical factors for both manufacturers and designers of semiconductor products.   Meeting yield and product cost targets is a continuous challenge, due to new device structures and increasingly complex process innovations introduced to achieve improved product performance at each new technology node.  Design for manufacturability (DFM) and design process technology co-optimization (DTCO) are widely used techniques that can ensure the successful delivery of both new processes and products in semiconductor manufacturing.   In this article, we will discuss how 3D (3 dimensional) DTCO can be used to improve product yield and accelerate product delivery dates in semiconductor manufacturing. read more…

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Pattern Dependence Process Modeling

By:   Joseph Ervin, Director – Semiconductor Process & Integration Engineering

First order process modeling can help tremendously with process setup and integration challenges that occur in a semiconductor fabrication flow, by visualizing process variation problems “virtually” prior to actual fabrication.  In some instances, a deeper level of complexity needs to be added to the process model to capture the effects of variation in the process.  read more…

Coventor Makes History (Museum)

Art piece with award

Organizers of the 53rd Design Automation Conference (DAC) hosted an art show to highlight the creativity and artistry that goes into much of the work in the electronics industry.  Coventor was honored with the grand prize for our 3D sculpture, which modeled 14nm FinFET Technology.

Here’s the background on how we came to make this piece.  read more…

IMEC Partner Technical Week Review

IMEC Partner Technical Week Review

By:   Aurélie Juncker, Semiconductor Process & Integration Engineer

a.Fully aligned Via with Cu recess approach - Gayle Murdoch, b. STT-RAM - Davide Crotti, c. N10 Supernova2 process - Matt Gallagher

a. Fully aligned Via with Cu recess approach – Gayle Murdoch, b. STT-RAM – Davide Crotti, c. N10 Supernova2 process – Matt Gallagher

In March 2016, Coventor was invited to the biannual Partner Technical Week (PTW) at IMEC in Leuven, Belgium. IMEC, a world-leading research group in nanotechnology, organizes their Partner Technical Week every 6 months to present scientific results to their partners. During this week, a number of specialists from IMEC’s many partner companies also discuss their progress in areas related to IMEC’s research. This event brings together a large number of engineers who are specialists in their domain, and provides an interesting forum to leverage the scientific knowledge gained by IMEC and its partners. read more…

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Introducing SEMulator3D Version 5.2

2016-05-10_12-51-08

By: Daniel Sieger, Lead Engineer, SEMulator3D Geometry and Michael Hargrove, Semiconductor Process & Integration Engineer

The SEMulator3D software platform has once again been updated and improved with significantly more features, making it the industry leader in semiconductor virtual fabrication.  read more…

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The Future of MEMS Sensor Design and Manufacturing

By:  Stephen Breit, VP of Engineering

I recently gave an invited talk at the IEEE Inertial Sensors 2016 symposium that discussed the future of commodity MEMS inertial sensor design and manufacturing. Inertial sensors comprise one of the fastest growing and most successful segments of the MEMS market. read more…

Will directed self-assembly pattern 14nm DRAM?

By: Mattan Kamon, PhD., Distinguished Technologist, R&D, Coventor

Matt's March 2016 Blog Graphic

But first, more generally, will directed self-assembly (DSA) join Extreme Ultraviolet (EUV) Lithography and next generation multi-patterning techniques to pattern the next memory and logic technologies?  Appealing to the wisdom of crowds, the organizers of the 2015 1st International DSA symposium recently surveyed the attendees, and nearly 75% believed DSA would insert into high volume manufacturing within the next 5 years, and nearly 30% predicted insertion within the next 2 years.   What is gating insertion?  The crowd rated defectivity as the most critical issue facing DSA.  This fact adds weight to memory being the first to be patterned with DSA.  This is because, as Roel Gronheid from IMEC pointed out last month at the SPIE Advanced Lithography conference [1], memory chips can tolerate single failing cells through redundancy and so can could tolerate higher defectivity in patterning (roughly 1 defect/cm2 compared to 0.01 defect/cm2 for logic).  Defectivity rates for DSA aren’t there yet (according to public information), but are rapidly approaching [2], [3]. read more…

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Advanced Lithography and Process Variation Modeling Using SEMulator3D

LER_Animation

Click on image to view animation of modeling

By:   Jimmy Gu, Coventor Technical Staff

One of the top and probably toughest challenges that process integrators are facing today in a silicon fab is process variability. As a former process integrator working hard to ramp up the yield of 22nm FinFET technology, I saw it first-hand. Looking back, I wish I was equipped with the SEMulator3D virtual fabrication platform, which is designed to address this type of process variability challenge. With the recent release of SEMulator3D 5.1, its process variability toolbox has just received a powerful new addition: the ability to model line edge roughness (LER) and line width roughness (LWR) in lithography. read more…