Posted in: Coventor Blog by Sandra Liu | Comments Off on Using Advanced Statistical Analysis to improve FinFET transistor performanceTuesday, September 19, 2017
By: Jimmy Gu, SP&I Staff Engineer
Trial and error wafer fabrication is commonly used to study the effect of process changes in the development of FinFET and other advanced semiconductor technologies. Due to the interaction of upstream unit process parameters (such as deposition conformality, etch anisotropy, selectivity) during actual fabrication, variations based upon process changes can be highly complex. Process simulators that mimic fab unit processes can now be used to model these complex interactions. They can also help process engineers identify important process and/or design parameters that drive certain critical targets such as CDs, yield limiting spacing, 3D design rule violations, resistance/capacitance, and other process and design issues. The number of possible parameters that affect device performance and yield can be quite large, so statistical analysis can provide useful insight and help identify critical performance parameters. Coventor’s SEMulator3D virtual fabrication (or process simulation) platform contains an analytics module for conducting virtual design-of-experiments and statistical analysis. I would like to use an example of a 14nm FinFET process flow in SEMulator3D to identify important process parameters that drive fin top CD, which is a key metric for transistor performance.
Posted in: Coventor Blog by Sandra Liu | Comments Off on Silicon Photonics: Solving Process Variation and Manufacturing ChallengesTuesday, August 8, 2017
By: Sandy Wen, Principal Engineer
As silicon photonics manufacturing gains momentum with additional foundry and 300mm offerings, process variation issues are coming to light. Variability in silicon processing affects the waveguide shape and can result in deviation in effective indices, propagation loss, and coupling efficiency from the intended design. In this article, we will highlight process variation issues that can occur in silicon photonics manufacturing and discuss techniques to mitigate these effects.
Figure 1. Example test photonic IC, with common elements such as waveguides, grating coupler, MZI, photodetector and fill pattern.
I’ve been doing a lot of interviewing as we grow our engineering team. I often say that hiring is the most important part of my job and also the hardest part. Like any sensible technology company, Coventor wants to hire the best engineers we can find. Good engineers love engineering. They love to build, to create, to innovate, to solve problems. Good engineers are methodical and persistent, but also bring engineering judgment and intuition that helps them arrive at solutions efficiently. Good engineers can’t help doing engineering – it’s who they are. Over the years, I’ve observed that good engineers are way more productive than mediocre engineers. The difference in productivity can be astounding, in excess of 2 or 3X for the best engineers. The trick, at least during the hiring process, is to discern which candidates are the good engineers. You can’t just look at academic degrees, skills claimed, or work experience to tell the difference. read more…
Posted in: Coventor Blog by Sandra Liu | Comments Off on The Future of MEMS Design: Making MEMS Design More Like CMOS DesignTuesday, July 18, 2017
By: Christine Dufour, MEMS PDK Program Manager
MEMS-based component suppliers want to rapidly ramp their designs into high-volume production. This demand is driving MEMS suppliers to focus on ways to more efficiently re-use established process steps, stacks or technology platforms. To meet this need, we see the emergence of standard MEMS technology and design platforms similar to those used in CMOS design.
The semiconductor industry and EDA vendors have established integrated design environments based on PDKs (Process Design Kits), standard cell libraries, memory architectures, and IP, to give easy access to the technology for IC designers and increase chances of first-pass successful silicon. Coventor’s vision is that the MEMS eco system and MEMS EDA software vendors should play a similar role in accelerating MEMS product development. read more…
Posted in: Coventor Blog by Marketing | Comments Off on CMOS Image Sensors (CIS): Past, Present & FutureWednesday, June 14, 2017
By: Sofiane Guissi, Semiconductor Process & Integration Engineer, Coventor
Over the last decade, CMOS Image Sensor (CIS) technology has made impressive progress. Image sensor performance has dramatically improved over the years, and CIS technology has enjoyed great commercial success since the introduction of mobile phones using on-board cameras. Many people, including scientists and marketing specialists, predicted 15 years earlier that CMOS image sensors were going to completely displace CCD imaging devices, in the same way that CCD devices displaced video capture tubes during the mid-1980’s. Although CMOS has a strong position in imaging today, it has not totally displaced CCD devices. On the other hand, the drive into CMOS technology has drastically increased the overall imaging market. CMOS image sensors have not only created new product applications, but have also boosted the performance of CCD imaging devices as well. In this paper, we describe the state-of-the-art in CMOS image sensor technology and discuss future perspectives.
By: Michael Hargrove, Semiconductor Process & Integration Engineer
Until EUV lithography becomes a reality, multiple patterning technologies such as triple litho-etch (LELELE), self-aligned double patterning (SADP), and self-aligned quadruple patterning (SAQP) are being used to meet the stringent patterning demands of advanced back-end-of-line (BEOL) technologies. For the 7nm technology node, patterning requirements include a metal pitch of 40nm or less. This narrow pitch requirement forces the use of spacer based pitch multiplication techniques. Unfortunately, these techniques have high process/lithography variability, which can severely impact RC and overall device performance.
Posted in: Coventor Blog by Sandra Liu | Comments Off on Photoresist shape in 3D: Understanding how small variations in photoresist shape significantly impact multi-patterning yieldWednesday, April 12, 2017
By: Mustafa B. Akbulut, Ph.D., Team Lead, Quality Assurance, Semiconductor Solutions
Things were easy for integrators when the pattern they had on the mask ended up being the pattern they wanted on the chip. Multi-patterning schemes such as Self-Aligned Double Patterning (SADP) and Self-Aligned Quadruple Patterning (SAQP) have changed that dramatically. Now, what you have on the mask determines only a part of what you will get at the end. read more…