Coventor Blog

Mid summer release of SEMulator3D adds more accuracy for deposition & CMP

By David M. Fried

Today we officially released SEMulator3D 2014.100. Typically, I wouldn’t be so excited about a “point release”, but this is clearly the biggest interim software release in recent SEMulator3D memory. We’ve added significant capability to an already industry-leading virtual fabrication platform. Many of the features of recent SEMulator3D releases have been focused on Etch enhancements. To complement these enhancements, we’ve stepped up the predictive accuracy of several other process models in SEMulator3D 2014.100, including Deposition and CMP.

The highlight of this release is a new Visibility-Limited Deposition model. This model dramatically improves the predictive accuracy for directional depositions, like Physical Vapor Deposition (PVD) and other plasma enhanced deposition processes. As with other process models in SEMulator3D, we’ve made this process simple to implement and calibrate using a reduced set of process parameters. The key features of this Visibility-Limited Deposition model are the “Source Sigma”, reflecting the directional distribution of the process, and the “Isotropic Ratio”, reflecting the non-visibility-limited component of the deposition process. This model enables a large variety of processes, with a wide range of results.

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Figure 1. Cross-sectional images of 3D models using Visibility-Limited Deposition model.

The modeling results above demonstrate the process capability range in 2D cross-sections, from very directional depositions in the top row to more conformal processes in the bottom row. Varying source distributions also exhibit different voiding and void shape during the deposition process. This capability will be used extensively in the modeling of state-of-the-art high-aspect ratio device geometries, including DRAM, 3D NAND Flash, MEMS and scaled FinFET CMOS.

SEMulator3D 2014.100 also includes a new Planarizing Deposition model, to more accurately reflect spin-on processes and flowable depositions. While these processes are meant to deliver a planar result, they inevitably retain some non-planarity due to underlying topography. The new Planarizing Deposition model delivers predictive accuracy for many different materials and processes, with various different planarizing behaviors.

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Figure 2. Cross-sectional images of 3D models using Planarizing Deposition model.

This model also accounts for deposition processes thinner than the underlying topography, resulting in exposed structures. This capability will be utilized to model several of the novel high-aspect-ratio fill processes as well as many of the innovative patterning film-stacks emerging in a semiconductor process environment still waiting for EUV.

There are several other features in SEMulator3D 2014.100, including a new CMP model that more accurately predicts dishing and over-polish behavior in the presence of complex underlying topography, and modeling performance/accuracy enhancements. We’ve also added a helpful process comparison tool that helps developers keep their flows accurately reflecting the fabrication process.

With this long list of features and enhancements, it’s pretty easy to see why I’m so excited for this interim release. These features answer the needs of our growing customer set, and address new complexities in advanced processes. I can’t wait to spend some time with our customers and exploit these capabilities to accelerate their technology development projects!

Linking Virtual Wafer Fabrication Modeling with Device-level TCAD Simulation

By Mike Hargrove

Most process/device simulation tools are TCAD-based. By this, I mean they share a common platform which connects the process simulator to the device simulator, usually using the same mesh structure. Most all of these TCAD tools are finite-element based, and the 3D final mesh structure is tetrahedral in nature. The mesh structure contains many nodes which define solution points for the numerous complex set of equations required to create the physical structure, in most cases a transistor, and solve for the electrical characteristics of the device. One of the drawbacks of TCAD is the computational time required to arrive at a solution – both process model solution and device electrical solution. A larger modeled area (e.g. multiple transistors and/or an SRAM cell) usually means longer simulation time.

Coventor’s virtual wafer fabrication approach addresses this challenge. Our process modeling platform combines with the statistical device TCAD suite of tools from Gold Standard Simulations, LTD. (GSS) to produce SRAM device-level simulation capability capturing real process-induced statistical variation. The ultimate objective of statistical device modeling is to capture the intrinsic variation of physically relevant process parameters. The combination of Coventor SEMulator3D process modeling capability and GSS statistical TCAD simulator GARAND fulfills this objective.
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What will the next 30 years of MEMS bring?

Steve Breit, VP Engineering
June, 2014

Coventor attended the Solid State Sensors, Actuators and Microsystems Conference last week, known simply as “Hilton Head” to the North American MEMS and nanotechnology community. This is a delightful conference held every two years at the same beachfront resort on Hilton Head Island, South Carolina. The location and single track of oral presentations create a congenial atmosphere for engaging with other participants.

At the opening, the conference chair Professor Mehran Mehregany of Case Western Reserve noted that this was the 30th anniversary of the conference and remarked on the incredible technical progress over that period. In 1984, the year of the first conference, MEMS products were only a gleam in the eyes of a select group of researchers. Today, MEMS ship in the billions and are ubiquitous in automobiles, mobile devices, and many other products. Professor Mehregany then asked the assembled micro- and nanotechnology research community a provocative question: Now that MEMS have become a reality, what should we do for the next 30 years? To help the research community answer this question, the organizers assembled a panel of four science fiction writers who shared their speculations on what might be possible in 30 years.
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The IoT bandwagon pulls into DAC

Every year at the Design Automation Conference (DAC), a common theme seems to arise. Most times it’s a chip design oriented or EDA-centric issue, like low power or system-level design, which makes sense since most attendees are deeply involved with design tools and the technical challenges they address. This year, I was pleased to see that the topic on everyone’s minds was a more customer centric one: the Internet of Things (IoT).

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IoT has certainly picked up a lot of momentum over the last year or so and everyone seems to want to jump on the bandwagon. The result is there is a lot of hype and confusion about exactly what IoT is. This is not uncommon for an emerging market segment and I am sure things will be more defined as it matures.

But there are some clear requirements for anything that falls into the IoT space, and that is good news for Coventor and our customers. A fundamental necessity is the need for MEMS and sensors – lots of them – to enable the IoT. These sensors will be located in entirely new areas, and as such, will require power, wireless sensor networks to transmit their data, and sophisticated algorithms to harness this data and bring new types of value and services to our lives.
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Challenges in 3D NAND Flash Processing

With 2D planar NAND flash hitting scaling issues at sub-20nm technology nodes, 3D NAND flash has become all the rage. Instead of restricting memory cells to a single plane and scaling the devices horizontally, memory cells can also be stacked vertically, allowing high cell density while side-stepping scaling issues (for now). Major NAND flash manufacturers have each developed their own designs and technology for 3D NAND flash, and with the addition of vertical cell stacking, new issues in 3D process integration arise.

For instance, in Samsung’s Terabit Cell Array Transistor (TCAT) technology [1], a memory cell array is formed of NAND flash strings with vertically-oriented channels and word lines arranged in planes. Of particular interest is the gate integration scheme: TCAT uses charge-trapping (SONOS/TANOS) with metal replacement gates, the combination which is expected to result in faster erase speed, wider threshold voltage margins, etc. The cell gates are created using a sacrificial nitride layer combined with a damascene process: the entire stack of SiO2/SiN layers is etched (“word line cut”) after staircase formation, then nitride is removed through wet etching with hot phosphoric acid, leaving behind gaps separated by the oxide. These gaps are then filled with dielectric and gate metal to create gate-all-around structures.
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Sneak Peak: New Capabilities for Micro Scanning and Projection Mirrors

By Gunar Lorenz, Director, System Level Simulation

Once again we are entering the final phase of a MEMS+ release cycle. We are tying up loose endsfor for another exciting release, over the summer, of our unique MEMS design software. I believe that the results of our latest research and development efforts will impress our users. You may ask: what’s so exiting about the new release? Well, it will surely require more than one blog to tell you about the many new features. For this blog, I will focus on the new capabilities in MEMS+ 5.0 that address the special design challenges presented by micro mirrors. Even if you are not working on micro mirror applications yourself, you may have heard about the new mini-projectors for smartphones from Fraunhofer or the new industrial devices from companies like Mirrorcle Technologies, Inc., Hamamatsu or Preciseley Microtechnology Corp: read more…