BEOL Issues At 10nm And 7nm

By Ed Sperling

Semiconductor Engineering sat down to discuss problems with the back end of line at leading-edge nodes with Craig Child, senior manager and deputy director for GlobalFoundries’ advanced technology development integration unit; Paul Besser, senior technology director at Lam Research; David Fried, CTO at Coventor; Chih Chien Liu, deputy division director for UMC’s advanced technology development Module Division; and Anton deVilliers, director of patterning technology and senior member of the technical staff at Tokyo Electron. What follows are excerpts of that conversation.

Experts at the table, part 1: Lines blur with middle of line as RC delay increases, reliability and yield become more difficult to achieve, and costs skyrocket.

Experts at the table, part 2: The impact and cost of air gap; reducing RC delay with liner-less approaches and cobalt; where EUV will make a dent…maybe.

Experts at the table, part 3: EUV, metallization, self-alignment, ALD, and the limits of copper.

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