Coventor’s FinFET Tipsheet for IEDM

Tech Design Forum Blog
December 4, 2012

At the upcoming IEDM, we’re likely to see a great deal of discussion about finFETs (Guide). Many groups are pursuing the goal of fully integrated finFET CMOS technology using a variety of approaches that have some similarities, but many key differences. Let’s examine a few of these differences, and explain the implications of the choices that device architects and process engineers are making.

Dr David M Fried is chief technology officer, semiconductors at Coventor, responsible for the company’s strategic direction and implementation of its SEMulator3D tool.

Bulk vs SOI substrates
The controversy about the best choice of substrate rages on. For planar devices, it focused mainly on cost vs. performance trade-offs. For finFETs, it takes on additional meaning. Starting substrate costs are still a factor, with SOI wafers costing three to six times as much as bulk Si wafers. However, transistor isolation in bulk finFETs requires a complex recessed shallow trench isolation process and additional isolation doping, whereas an SOI substrate has inherent fin isolation thanks to its buried oxide layer. The implants needed to isolate the finFET on bulk add cost, as well as threatening device performance due to leakage, capacitance and mobility degradation effects. That’s not to say that building SOI finFETs is easy. Process variations that over-etch the buried oxide could lead to failed devices, whereas at least bulk finFETs are well anchored to the substrate.

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