Next Challenge: Contact Resistance

By Mark Lapedus

In chip scaling, there is no shortage of challenges. Scaling the finFET transistor and the interconnects are the biggest challenges for current and future devices. But now, there is another part of the device that’s becoming an issue—the contact.

Typically, the contact doesn’t get that much attention, but the industry is beginning to worry about the resistance in the contacts, or contact resistance, in leading-edge chip designs.

Basically, a chip has two main structures—the transistor and interconnects. The transistor, which serves as a switch in a device, resides on the bottom of the structure. On top of the transistor, there are several levels. These levels consist of tiny copper wiring schemes, or interconnects, which are connected throughout the chip.

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