By: Michael Hargrove, SP&I Engineer
The semiconductor technology simulation world is typically divided into device-level TCAD (technology CAD) and circuit-level compact modeling. Larger EDA companies provide high-level design simulation tools that perform LVS (layout vs. schematic), DRC (design rule checking), and many other software solutions that facilitate the entire design process at the most advanced technology nodes. In this blog, I’d like to focus on the design of silicon-level connections between devices and wires in the backend-of-line (BEOL). These connections run across chips and connect various nodes to each other, and ultimately form circuits on the device. read more…
By Christine Dufour (Coventor) and Viraja and Sharma (X-FAB)
Pressure Sensor (Courtesy: X-FAB)
New MEMS-based products are constantly emerging, fueled by the Internet of Things (IoT), autonomous driving, smart manufacturing and healthcare applications. The MEMS pressure sensor market is no exception to this trend1. Its growth has been driven mainly by automotive applications such as tire pressure management system (TPMS) regulations in China, fuel and ignition systems, thermal systems, oil-pressure monitoring, and indoor and outdoor navigation systems. Easy to customize and integrate, miniature, sensitive, accurate and low-power MEMS devices are especially well-suited to the accuracy, power consumption, sensitivity and miniaturization that pressure sensors require. read more…
Coventor / Lam is participating!
Coventor is exhibiting! See us at booth #835.
By Ed Sperling and Mark LaPedus
Packaging is emerging as one of the most critical elements in semiconductor design, but it’s also proving difficult to master both technically and economically.
The original role of packaging was simply to protect the chips inside, and there are still packages that do just that. But at advanced nodes, and with the integration of heterogeneous components built using different manufacturing processes, packaging is taking on a much broader and more strategic role. Many of the new packages are application-specific, and they are an integral part of the system architecture. They can help channel heat, improve performance, help to reduce power, and even safeguard signal integrity.
Read the full article here
By: Benjamin Vincent, Ph.D., Staff Engineer, Semiconductor Process & Integration
Advanced logic scaling has created some difficult technical challenges, including a requirement for highly dense patterning. Imec recently confronted this challenge, by working toward the use of Metal 2 (M2) line patterning with a 16 nm half-pitch for their 7nm node (equivalent to a 5nm foundry node). Self-Aligned Quadruple Patterning (SAQP) was investigated as an alternative path to Extreme Ultra-Violet (EUV) lithography for this line patterning application. At the 2019 SPIE Advanced Lithography conference, Coventor personnel demonstrated how virtual process modeling (combined with advanced process control) could provide enhanced patterning yield and enable SAQP patterning at this tight pitch (See Complete White Paper). A summary of the team’s methodology and results are included below. read more…