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A Study of Next Generation CFET Process Integration Options

By: Benjamin Vincent, SP&I Engineer

Decision making is a critical step in semiconductor technology development. R&D semiconductor engineers must consider different design and process options early in the development of a next-generation technology. Established techniques such as Failure Mode and Effect Analysis (FMEA) can be used to select among the most promising design and process choices. Once specific design and process methodologies are chosen, time and money is then spent on first tape-out and wafer processing.

How can engineers ensure that they have selected the optimal design and technology development pathway prior to tape-out? How do they know that critical technology decisions were made properly? read more…

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Making Random Variation Less Random

The economics for random variation are changing, particularly at advanced nodes and in complex packaging schemes.  Random variation always will exist in semiconductor manufacturing processes, but much of what is called random has a traceable root cause. The reason it is classified as random is that it is expensive to track down all of the various quirks in a complex manufacturing process or in materials or unusual use cases. In the past, most of these have not impacted yield, but the equation is beginning to change for a number of reasons

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New Product Announcement – CoventorMP 1.2

We are very pleased to announce the release of our latest MEMS design software, CoventorMP 1.2. This release has been enriched to improve the accuracy of device models and extend the types of devices that can be modeled. It contains enhanced model construction capabilities, a number of great new analysis functions, some significant performance improvements, advances in 3rd-party support and other exciting new features. read more…

How FinFET Device Performance is Affected by Epitaxial Process Variations

By: Jacky Huang and Yu De Chen

As the need to scale transistors to ever-smaller sizes continues to press on technology designers, the impact of parasitic resistance and capacitance can approach or even outpace other aspects of transistor performance, such as fringing capacitance or source drain resistance. The total resistance in a device is comprised of two components: internal resistance (which is essentially channel resistance) and external resistance (which is the combination of source drain resistance and metal contact resistance). As key feature sizes shrink at advanced technology nodes, external resistance plays an increasingly important role. Simulation-based design-technology co-optimization (DTCO) offers us some insight into the sensitivity of FinFET device performance to changes in process flows that impact external resistance. read more…

Goldilocks Process Windows: Coventor’s Latest SEMulator3D Helps to Determine “Just Right”

One of the tricky bits when launching a new process is figuring out what the process window is.  For anyone new to the concept, the window is the range of variation that’s allowable for a given process parameter. Go outside that range, and a die – or a wafer – or a lot – may fail.

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Video: “Process Window Optimization”

David Fried, vice president of computational products at Lam Research, examines increasing process variation and interactions between various types of variation, why different approaches are necessary to improve yield and continue scaling.

How to deal with variation, and interactions between various types of variation.

[Video Attribution: Semiconductor Engineering]

Advanced Patterning Techniques for 3D NAND Devices

By: Yu De Chen, Jacky Huang

Introduction

Driven by Moore’s law, memory and logic semiconductor manufacturers pursue higher transistor density to improve product cost and performance [1]. In NAND Flash technologies, this has led to the market dominance of 3D structures instead of 2D planar devices. Device density can be linearly increased by increasing stack layer counts in a 3D NAND device [2]. At the same time, patterning scheme optimization can also enhance 3D NAND effective device density. In this discussion, we will analyze various patterning schemes for staircase and slit structures at different TCAT (Terabit Cell Array Transistor) 3D NAND nodes. We will compare these schemes to understand their impact on effective transistor density. The schemes and data used in this study are based upon (or inferred from) tear down reports published by TechInsights®. Variations in patterning schemes, and the resulting virtual structures, were modeled using the SEMulator3D® semiconductor platform. read more…

Node Within A Node

Reducing process margin could provide an entire node’s worth of scaling benefits.

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