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Everything You Need to Know about FDSOI Technology – Advantages, Disadvantages, and Applications of FDSOI

By: Sofiane Guissi, Semiconductor Process & Integration Engineer

Over the past decades, transistor feature size has continuously decreased, leading to an increase in performance and a reduction in power consumption. Consumers have reaped the benefits, with superior electronic devices that have become increasingly useful, valuable, faster and more efficient. In recent years, as transistor feature size has shrunk below 10nm, it has become progressively more difficult to meet the many challenges of next generation technology.

Fully Depleted Silicon on Insulator (FDSOI) CMOS Transistors

FDSOI technology offers a promising answer to these challenges. Fully Depleted Silicon on Insulator, or FDSOI, is a planar process technology that delivers the benefits of reduced silicon geometries while simplifying the manufacturing process. This process technology relies on two primary innovations. First, an ultra-thin layer of insulator, called the buried oxide (BOX), is positioned on top of the base silicon. Then, a very thin silicon film is used to form a transistor channel. Due to the thin film silicon structure, there is no need to dope the channel, thus making the transistor “fully depleted.”

Figure 1 (left) shows a fully depleted (FD) 2D SOI wafer. At center is an illustration of an FDSOI transistor structure (source:  ST Microelectronics). An actual 28nm FDSOI Transistor is shown on the far right (source:  Qing Liu et. al, 2011 VLSI Conference).

Figure 1: From SOI wafer to FDSOI Transistor

Figure 1: From SOI wafer to FDSOI Transistor

FDSOI CMOS Transistor: Key Advantages

FDSOI technology exhibits major benefits for advanced and future technology nodes. Thin silicon film technology allows superior electrostatic control of the gate on the channel of the transistor, compared to conventional architectures (like FinFETs). This control is accomplished by efficient body biasing, which provides faster switching speeds, and provides a good compromise between performance and power consumption at the circuit level.

FDSOI remains a planar technology, which makes it easier to transition from conventional technologies; manufacturability is simplified compared to the manufacture of FinFET devices. The use of thin buried insulator layers in FDSOI offers the ability to dynamically modulate the threshold voltage of the devices and obtain the best compromise between performance and power consumption.

Figure 2 summarizes the main benefits of FDSOI Transistor and technology.

Figure 2: Main Benefits of FDSOI

Figure 2: Main Benefits of FDSOI
DIBL -> Drain Induced Barrier Lowering
RDF ->  Random Dopant Fluctuation
FBB & RBB -> Forward & Reverse Body Biasing
GP -> Ground Plane

FDSOI APPLICATIONS: Benefits by Market Segment

Automotive is an emerging application area for FDSOI technology, due to its inherent radiation tolerance. IoT products are also expected to be a big market for FDSOI, due to superior RF and analog performance coupled with low power, high performance and relative ease of design. Other application areas including networking infrastructure, machine learning, and consumer multimedia applications.

Further Reading

In summary, FDSOI technology provides improved speed, reduced power and a simpler manufacturing process compared to bulk silicon technologies. It delivers a good power/performance/cost tradeoff compared to both bulk and FinFET technologies, which has led to adoption in automotive, IoT and other applications. The clear roadmap to improve FDSOI performance provides a path to develop the next generation of high performance, low power semiconductor devices. If you are insterested in learning more about FDSOI technology, you may read the full paper here.

Microelectronics Sector Extends AI from Pattern Recognition to Prediction and Control

By Paula Doe

The fast-maturing infrastructure now enabling analysis of exponentially larger data volumes brings the microelectronics industry to an inflection point, where the winning companies will be the first to master the use of this data to solve the industry’s emerging challenges. SEMI expands its coverage of these vital issues with a Smart Manufacturing Pavilion and three days of talks SEMICON West, July 10-12 in San Francisco.

While deep learning is starting to be applied to image recognition for wafer inspection, it is also being considered for sequential pattern recognition in order to evaluate equipment parameter traces. The next emerging applications will start to use those learned patterns to predict outcomes, and then use those predictions to automate process control. One early application of deep learning is IC process development.

read the full article here

MEMS Design Contest Winners

By Bryon Moyer

Two years ago at the annual DATE conference in Europe, a MEMS design contest was announced. Sponsored by Reutlingen University, Coventor, X-Fab, and Cadence, the goal was to stimulate creative ideas for MEMS technology. The sponsors each had a part: Coventor and Cadence provided tools for the design process, and X-Fab signed up to build the winning design. Reutlingen University helped with the organizing efforts.

Well, the winners were recently announced, and we’re going to look through the projects of the top three contestants. The problems they tackle vary widely, and they’re not necessarily what you might be expecting. The projects are interesting in their own right, which is why we’re having this little chat.

read the full article here

Practical Methods to Overcome the Challenges of 3D Logic Design

By:  Benjamin Vincent, Ph.D., Staff Engineer, Semiconductor Process & Integration

What should you do If you don’t have enough room on your floor to store all your old boxes? Luckily, we live in a 3D world, and you can start stacking them on top of each other!

The Challenge: How can we shrink logic devices?

Logic designers are currently facing even bigger challenges than you might be having in tidying up your storage area. Not only are logic cells highly packed together already, but in addition their sizes are constantly required to shrink. Logic designers can increase the density of devices by re-engineering logic to generate new white space areas on their logic cells. This white space can be subsequently removed, in effect increasing the density of the device. When component (transistor) level scaling cannot shrink sizes any further, designers need to find other scaling boosters. Luckily, logic designers have another alternative to increase the density of their designs. We live in a 3D world, and we can think about designing in 3 dimensions to increase device performance over that of current 2D designs. read more…

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Dealing With Resistance In Chips

By MARK LAPEDUS

Chipmakers continue to scale the transistor at advanced nodes, but they are struggling to maintain the same pace with the other two critical parts of the device—the contacts and interconnects.

That’s beginning to change, however. In fact, at 10nm/7nm, chipmakers are introducing new topologies and materials such as cobalt, which promises to boost the performance and reduce unwanted resistance in chips. It’s still too early to say if the changes will work. Early reviews are mixed.

To be sure, though, there is an inflection point taking place in leading-edge chips, which consist of three parts—the transistor, contacts and interconnects. The transistor resides on the bottom of the structure and serves as a switch. The interconnects, which reside on the top of the transistor, consist of tiny copper wiring schemes that transfer electrical signals from one transistor to another.

read the full article here

Big Trouble At 3nm

By MARK LAPEDUS

As chipmakers begin to ramp up 10nm/7nm technologies in the market, vendors are also gearing up for the development of a next-generation transistor type at 3nm.

Some have announced specific plans at 3nm, but the transition to this node is expected to be a long and bumpy one, filled with a slew of technical and cost challenges. For example, the design cost for a 3nm chip could exceed an eye-popping $1 billion. In addition, there are also several uncertainties at 3nm that could change everything overnight.

That hasn’t sidelined anyone yet, however. Samsung and GlobalFoundries separately announced plans to develop a new transistor technology called a nanosheet FET, with so-called variable widths at 3nm. Samsung, for one, hopes to deliver a PDK (version .01) by 2019, with plans to move into production by 2021. Meanwhile, TSMC is exploring nanosheet FETs and a related technology, nanowire FETs, at 3nm, but it has not announced its final plans. Intel, meanwhile, isn’t talking about its plans.

read the full article here

LiDAR: How MEMS is enabling the new trend in spatial sensing

By: Coventor Marketing

You’ve probably heard a lot about LiDAR. It stands for Light Detection and Ranging, and it’s playing a central role in many emerging technologies like autonomous vehicles, robotics and home automation. What sets LiDAR apart from other spatial sensing technologies is the precision and density of the distance data than can be attained from such sensors. read more…

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SEMICON West Preview: Smart Microelectronics Manufacturing Builds the Infrastructure to Enable AI Applications

By Paula Doe

The fast-maturing hardware and software that are enabling practical applications of equipment intelligence and machine learning mean disruptive change for microelectronics manufacturing. But first comes the basic work of building the basic infrastructure, figuring out IP separation, and learning to solve physical problems in the digital world.

Just how much can the semiconductor industry leverage industrial IoT practices from other industries? Common wisdom may be that industrial software solutions aren’t well suited to the IC sector’s complex needs. But GE Digital enterprise account executive Luke Smaul, currently working with Intel, argues that semiconductor fabs and toolmakers are dealing with similar issues as GE did when it first started working with Delta Airlines to monitor the GE engines on Delta planes. Smaul will speak at SEMICON West about GE’s work with Intel over the past few years and, in particular, how its solution for cloud security and IP separation can work for ICs.

read the full article here