Blog


Innovative Solutions to Increase 3D NAND Flash Memory Density

By: Timothy Yang, Software Applications Engineer

Introduction

3D NAND flash memory has enabled a new generation of non-volatile solid-state storage useful in nearly every electronic device imaginable. 3D NAND can achieve data densities exceeding those of 2D NAND structures, even when fabricated on later generation technology nodes.  The methods used to increase storage capacity come with potentially significant tradeoffs in memory storage, structural stability, and electrical characteristics. This post will discuss the manufacturing challenges of 3D NAND structures, as well as techniques to advance the data density of 3D NAND devices, studied in our recent work.

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Analyzing Worst-Case Silicon Photonic Device Performance Through Process Modeling and Optical Simulation

By:  Ryan Miller, Senior Software QA Engineer

This blog is a summary of a technical and business review of FDSOI technology. Read the full paper here.

Background

Silicon photonics is an emerging and rapidly-expanding design platform that promises to enable higher-bandwidth communication and other applications. One of the best qualities of silicon photonics is its ability to leverage existing CMOS fabrication equipment and process flows. However, this means that it is subject to the same process defects and variations. Previous blog posts [References 1,2] have detailed the power of utilizing process simulation to explore the impact of fabrication defects on photonic integrated circuit (PIC) component performance.

Design for manufacturability (DFM) models for silicon photonics are not as mature as their CMOS counterparts. However, it is possible to use virtual fabrication and optical simulation experiments to capture worst-case scenarios for a given device and process defect. This can help answer the question, “Given a window of fabrication variability, what is the worst-case scenario on device performance for a silicon photonic device?” We will explore the effect of a common manufacturing defect that occurs during lithography and etch processing, known as line edge roughness (LER), on photonic (PIC) device performance.  In this study, we will analyze the effect of LER on a Y-branch splitter [Reference 3] using semiconductor process modeling (virtual fabrication) and optical simulation. The results being presented are a subset of results obtained during a joint collaborative effort between Coventor and Professor Duane Boning’s group at MIT.  Additional detail regarding this study can be found in Reference [4]. read more…

IEEE INERTIALS 2019 – April 1-5, 2019 – NAPLES, FL


Coventor is exhibiting!

What’s The Right Path For Scaling?

By Mark Lapedus

The growing challenges of traditional chip scaling at advanced nodes are prompting the industry to take a harder look at different options for future devices.S
caling is still on the list, with the industry laying plans for 5nm and beyond. But less conventional approaches are becoming more viable and gaining traction, as well, including advanced packaging and in-memory computing. Some options are already here, while others are still in R&D and require more funding to get off the ground. Some may never work.

read the full article here

SPIE Advanced Lithography 2019 – February 24-28, 2019 – San Jose, CA

Coventor is exhibiting! See us at booth #323/325. Coventor will be presenting a keynote on:

  • “Combining equipment sensors and control hardware with metrology and advanced computational methods for comprehensive 3D process control”

Coventor will also be giving oral presentations on:

  • “Self-aligned fin cut last patterning scheme for fin arrays of 24nm pitch and beyond”
  • “Self-aligned quadruple patterning assessment for 16nm half-pitch metal 2 BEOL using virtual fabrication”
  • “Backside power delivery as a scaling knob for future systems”

3D NAND: Challenges beyond 96-Layer Memory Arrays

By: Steve Shih-Wei Wang, PhD, SP&I Engineer

Unlike scaling practices in 2D NAND technology, the direct way to reduce bit costs and increase chip density in 3D NAND is by adding layers. In 2013, Samsung shipped the first V-NAND product using 24 layers and MLC [1]. Five years later, in 2018, vendors of 3D-NAND have all announced production plans for 96-Layer NAND using TLC [2]. According to recent news reports, vendors are already working on next generation 3D NAND that contains even more layers. What are the 3D NAND’s process challenges, and what might be its ceiling, as increasing numbers of layers are used?

Figure 1: 3D NAND Memory Array and Key Process Challenges (Source: Lam Research)

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Variation’s Long, Twisty Tail Worsens At 7/5nm

By Ed Sperling

Variation is becoming a bigger challenge at each new node, but not just for obvious reasons and not always from the usual sources. Nevertheless, dealing with these issues takes additional time and resources, and it can affect the performance and reliability of those chips throughout their lifetimes.

read the full article here

MEMS 2019 – January 27-31, 2019 – Soeoul, Korea

Coventor is exhibiting!

Visit us at booth #44.