Blog


3D NAND: Challenges beyond 96-Layer Memory Arrays

By: Steve Shih-Wei Wang, PhD, SP&I Engineer

Unlike scaling practices in 2D NAND technology, the direct way to reduce bit costs and increase chip density in 3D NAND is by adding layers. In 2013, Samsung shipped the first V-NAND product using 24 layers and MLC [1]. Five years later, in 2018, vendors of 3D-NAND have all announced production plans for 96-Layer NAND using TLC [2]. According to recent news reports, vendors are already working on next generation 3D NAND that contains even more layers. What are the 3D NAND’s process challenges, and what might be its ceiling, as increasing numbers of layers are used?

Figure 1: 3D NAND Memory Array and Key Process Challenges (Source: Lam Research)

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Variation’s Long, Twisty Tail Worsens At 7/5nm

By Ed Sperling

Variation is becoming a bigger challenge at each new node, but not just for obvious reasons and not always from the usual sources. Nevertheless, dealing with these issues takes additional time and resources, and it can affect the performance and reliability of those chips throughout their lifetimes.

read the full article here

MEMS 2019 – January 27-31, 2019 – Soeoul, Korea

Coventor is exhibiting!

Visit us at booth #44.

SEMICON Korea 2019 – January 23-25, 2019 – Seoul, Korea

Coventor will be giving the following talks:

  • “Process variation studies and the impact on electrical performance”
  • “Smart Manufacturing and Machine Learning: Process Control in 3D”

IEDM 2018 – December 1-5, 2018 – San Francisco, CA

Coventor is exhibiting!

Using AI In Chip Manufacturing

By Ed Sperling

David Fried, CTO at Coventor, a Lam Research Company, sat down with Semiconductor Engineering to talk about how AI and Big Data techniques will be used to improve yield and quality in chip manufacturing. What follows are excerpts of that conversation.

SE: We used to think about manufacturing data in terms of outliers, but as tolerances become tighter at each new node that data may need to be examined even within what is considered the normal range. What’s the impact of that on manufacturing?

Fried: When I started in CMOS at 200mm, there was some data on the tools in the fab, but by and large, we were losing it as soon as it was created. When we went to 300mm, we got better at putting sensors on tools, generating data, and in some cases looking at it.

read the full article here

A Review of Silicon Photonics: Using Process Simulation to Design Silicon Photonics Devices

By: Michael Hargrove, SP&I Engineer

With the end of Moore’s Law rapidly approaching, or as some folks say – “already here”, new applications of older technologies are gaining attention. One specific area of interest is photonics. The National Center for Optics and Photonic Education defines photonics as the technology of generating and harnessing light and other forms of radiant energy whose quantum unit is the photon. It can also be defined as the science and application of light. Photonic applications use the photon in the same way that electronic applications use the electron. So, it’s natural to think of photonic applications in a similar manner as we think of electronic applications. The connection back to Moore’s Law is that we want to integrate photonic structures on a typical silicon wafer, utilizing Si-based technology that the industry has been continually shrinking and improving. This aspiration has led to the creation of silicon photonics technology, where photonics structures are built directly onto silicon wafers. read more…

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Everything You Need to Know about FDSOI Technology – Advantages, Disadvantages, and Applications of FDSOI

By: Sofiane Guissi, Semiconductor Process & Integration Engineer

This blog is a summary of a technical and business review of FDSOI technology. Read the full paper here.

Over the past decades, transistor feature size has continuously decreased, leading to an increase in performance and a reduction in power consumption. Consumers have reaped the benefits, with superior electronic devices that have become increasingly useful, valuable, faster and more efficient. In recent years, as transistor feature size has shrunk below 10nm, it has become progressively more difficult to meet the many challenges of next generation technology. read more…