Blog


Using AI In Chip Manufacturing

By Ed Sperling

David Fried, CTO at Coventor, a Lam Research Company, sat down with Semiconductor Engineering to talk about how AI and Big Data techniques will be used to improve yield and quality in chip manufacturing. What follows are excerpts of that conversation.

SE: We used to think about manufacturing data in terms of outliers, but as tolerances become tighter at each new node that data may need to be examined even within what is considered the normal range. What’s the impact of that on manufacturing?

Fried: When I started in CMOS at 200mm, there was some data on the tools in the fab, but by and large, we were losing it as soon as it was created. When we went to 300mm, we got better at putting sensors on tools, generating data, and in some cases looking at it.

read the full article here

A Review of Silicon Photonics: Using Process Simulation to Design Silicon Photonics Devices

By: Michael Hargrove, SP&I Engineer

With the end of Moore’s Law rapidly approaching, or as some folks say – “already here”, new applications of older technologies are gaining attention. One specific area of interest is photonics. The National Center for Optics and Photonic Education defines photonics as the technology of generating and harnessing light and other forms of radiant energy whose quantum unit is the photon. It can also be defined as the science and application of light. Photonic applications use the photon in the same way that electronic applications use the electron. So, it’s natural to think of photonic applications in a similar manner as we think of electronic applications. The connection back to Moore’s Law is that we want to integrate photonic structures on a typical silicon wafer, utilizing Si-based technology that the industry has been continually shrinking and improving. This aspiration has led to the creation of silicon photonics technology, where photonics structures are built directly onto silicon wafers. read more…

Tagged

2018 International Conference on Solid State Devices and Materials (SSDM2018) – September 9-13, 2018, Tokyo, Japan

Coventor will be giving an oral presentation on “CMOS Area Scaling and the Need for High Aspect Ratio Vias

Everything You Need to Know about FDSOI Technology – Advantages, Disadvantages, and Applications of FDSOI

By: Sofiane Guissi, Semiconductor Process & Integration Engineer

This blog is a summary of a technical and business review of FDSOI technology. Read the full paper here.

Over the past decades, transistor feature size has continuously decreased, leading to an increase in performance and a reduction in power consumption. Consumers have reaped the benefits, with superior electronic devices that have become increasingly useful, valuable, faster and more efficient. In recent years, as transistor feature size has shrunk below 10nm, it has become progressively more difficult to meet the many challenges of next generation technology. read more…

Microelectronics Sector Extends AI from Pattern Recognition to Prediction and Control

By Paula Doe

The fast-maturing infrastructure now enabling analysis of exponentially larger data volumes brings the microelectronics industry to an inflection point, where the winning companies will be the first to master the use of this data to solve the industry’s emerging challenges. SEMI expands its coverage of these vital issues with a Smart Manufacturing Pavilion and three days of talks SEMICON West, July 10-12 in San Francisco.

While deep learning is starting to be applied to image recognition for wafer inspection, it is also being considered for sequential pattern recognition in order to evaluate equipment parameter traces. The next emerging applications will start to use those learned patterns to predict outcomes, and then use those predictions to automate process control. One early application of deep learning is IC process development.

read the full article here

MEMS Design Contest Winners

By Bryon Moyer

Two years ago at the annual DATE conference in Europe, a MEMS design contest was announced. Sponsored by Reutlingen University, Coventor, X-Fab, and Cadence, the goal was to stimulate creative ideas for MEMS technology. The sponsors each had a part: Coventor and Cadence provided tools for the design process, and X-Fab signed up to build the winning design. Reutlingen University helped with the organizing efforts.

Well, the winners were recently announced, and we’re going to look through the projects of the top three contestants. The problems they tackle vary widely, and they’re not necessarily what you might be expecting. The projects are interesting in their own right, which is why we’re having this little chat.

read the full article here

Practical Methods to Overcome the Challenges of 3D Logic Design

By:  Benjamin Vincent, Ph.D., Staff Engineer, Semiconductor Process & Integration

What should you do If you don’t have enough room on your floor to store all your old boxes? Luckily, we live in a 3D world, and you can start stacking them on top of each other!

The Challenge: How can we shrink logic devices?

Logic designers are currently facing even bigger challenges than you might be having in tidying up your storage area. Not only are logic cells highly packed together already, but in addition their sizes are constantly required to shrink. Logic designers can increase the density of devices by re-engineering logic to generate new white space areas on their logic cells. This white space can be subsequently removed, in effect increasing the density of the device. When component (transistor) level scaling cannot shrink sizes any further, designers need to find other scaling boosters. Luckily, logic designers have another alternative to increase the density of their designs. We live in a 3D world, and we can think about designing in 3 dimensions to increase device performance over that of current 2D designs. read more…

Tagged , , , , ,

Dealing With Resistance In Chips

By MARK LAPEDUS

Chipmakers continue to scale the transistor at advanced nodes, but they are struggling to maintain the same pace with the other two critical parts of the device—the contacts and interconnects.

That’s beginning to change, however. In fact, at 10nm/7nm, chipmakers are introducing new topologies and materials such as cobalt, which promises to boost the performance and reduce unwanted resistance in chips. It’s still too early to say if the changes will work. Early reviews are mixed.

To be sure, though, there is an inflection point taking place in leading-edge chips, which consist of three parts—the transistor, contacts and interconnects. The transistor resides on the bottom of the structure and serves as a switch. The interconnects, which reside on the top of the transistor, consist of tiny copper wiring schemes that transfer electrical signals from one transistor to another.

read the full article here