David Fried, vice president of computational products at Lam Research, examines increasing process variation and interactions between various types of variation, why different approaches are necessary to improve yield and continue scaling.
How to deal with variation, and interactions between various types of variation.
Posted in: Coventor Blog by Sandra Liu | Comments Off on Advanced Patterning Techniques for 3D NAND DevicesThursday, August 1, 2019
By: Yu De Chen, Jacky Huang
Driven by Moore’s law, memory and logic semiconductor manufacturers pursue higher transistor density to improve product cost and performance . In NAND Flash technologies, this has led to the market dominance of 3D structures instead of 2D planar devices. Device density can be linearly increased by increasing stack layer counts in a 3D NAND device . At the same time, patterning scheme optimization can also enhance 3D NAND effective device density. In this discussion, we will analyze various patterning schemes for staircase and slit structures at different TCAT (Terabit Cell Array Transistor) 3D NAND nodes. We will compare these schemes to understand their impact on effective transistor density. The schemes and data used in this study are based upon (or inferred from) tear down reports published by TechInsights®. Variations in patterning schemes, and the resulting virtual structures, were modeled using the SEMulator3D® semiconductor platform. read more…
Reducing process margin could provide an entire node’s worth of scaling benefits.
Enough margin exists in manufacturing processes to carve out the equivalent of a full node of scaling, but shrinking that margin will require a collective push across the entire semiconductor manufacturing supply chain.
Posted in: Press Coverage by Karin Conti | Comments Off on ES Design West Opens July 9 with Exhibit Floor Showcasing Companies that Span Entire Electronic System Design EcosystemMonday, July 1, 2019
IBM’s Q Quantum Computer a Featured Highlight
MILPITAS, CALIF. – July 1, 2019 – The exhibit floor at ES Design West will be a showplace of companies that span the entire electronic system design ecosystem including IP, EDA, embedded software, design services, design infrastructure and the cloud presenting system-centric commercial solutions for complex chip design.
Posted in: Coventor Blog by Marketing | Comments Off on Controlling Variability using Semiconductor Process Window OptimizationTuesday, June 25, 2019
By: Benjamin Vincent, Software Applications Engineer
Courtesy: Lam Research
To ensure success in semiconductor technology development, process engineers must set the allowed ranges for wafer process parameters. Variability must be controlled, so that final fabricated devices meet required specifications. These specifications include critical dimensions, electrical performance requirements, and other device characteristics. Pre-production or ramp-up production Si wafers, which are processed in the fab but not yet optimized, are the usual source of test data needed to understand and control this variability. read more…