Video: “Process Window Optimization”

David Fried, vice president of computational products at Lam Research, examines increasing process variation and interactions between various types of variation, why different approaches are necessary to improve yield and continue scaling.

How to deal with variation, and interactions between various types of variation.

[Video Attribution: Semiconductor Engineering]

Advanced Patterning Techniques for 3D NAND Devices

By: Yu De Chen, Jacky Huang


Driven by Moore’s law, memory and logic semiconductor manufacturers pursue higher transistor density to improve product cost and performance [1]. In NAND Flash technologies, this has led to the market dominance of 3D structures instead of 2D planar devices. Device density can be linearly increased by increasing stack layer counts in a 3D NAND device [2]. At the same time, patterning scheme optimization can also enhance 3D NAND effective device density. In this discussion, we will analyze various patterning schemes for staircase and slit structures at different TCAT (Terabit Cell Array Transistor) 3D NAND nodes. We will compare these schemes to understand their impact on effective transistor density. The schemes and data used in this study are based upon (or inferred from) tear down reports published by TechInsights®. Variations in patterning schemes, and the resulting virtual structures, were modeled using the SEMulator3D® semiconductor platform. read more…

Node Within A Node

Reducing process margin could provide an entire node’s worth of scaling benefits.

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2020 SPIE Advanced Lithography Conference – San Jose, CA – February 23-27, 2020

See us at booth #323/325!


Week In Review: Manufacturing, Test

The Semicon West trade show took place this week in San Francisco. There were a slew of announcements at the event. Applied Materials, Coventor, Intel, KLA and others made various announcements.

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Coventor Adds Process Optimization Features to SEMulator3D 8.0

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For Immediate Distribution
For more information, contact:
Toni Sottak
(408) 876-4418

Coventor Adds Process Optimization Features to SEMulator3D® 8.0

New Features Enable SEMulator3D 8.0 to Address Both Process Modeling and Device Analysis for Better Insight into Advanced Semiconductor Technology Development

New in SEMulator3D 8.0, powerful new process simulation and analytics capabilities accelerate semiconductor technology development and Design-Technology Co-Optimization (DTCO).

New in SEMulator3D 8.0, powerful new process simulation and analytics capabilities accelerate semiconductor technology development and Design-Technology Co-Optimization (DTCO).

read more…

ES Design West Opens July 9 with Exhibit Floor Showcasing Companies that Span Entire Electronic System Design Ecosystem

IBM’s Q Quantum Computer a Featured Highlight

MILPITAS, CALIF. – July 1, 2019 – The exhibit floor at ES Design West will be a showplace of companies that span the entire electronic system design ecosystem including IP, EDA, embedded software, design services, design infrastructure and the cloud presenting system-centric commercial solutions for complex chip design.


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Controlling Variability using Semiconductor Process Window Optimization

By: Benjamin Vincent, Software Applications Engineer


Courtesy:  Lam Research

To ensure success in semiconductor technology development, process engineers must set the allowed ranges for wafer process parameters. Variability must be controlled, so that final fabricated devices meet required specifications. These specifications include critical dimensions, electrical performance requirements, and other device characteristics. Pre-production or ramp-up production Si wafers, which are processed in the fab but not yet optimized, are the usual source of test data needed to understand and control this variability. read more…