By: Steve Shih-Wei Wang, PhD, SP&I Engineer
Unlike scaling practices in 2D NAND technology, the direct way to reduce bit costs and increase chip density in 3D NAND is by adding layers. In 2013, Samsung shipped the first V-NAND product using 24 layers and MLC . Five years later, in 2018, vendors of 3D-NAND have all announced production plans for 96-Layer NAND using TLC . According to recent news reports, vendors are already working on next generation 3D NAND that contains even more layers. What are the 3D NAND’s process challenges, and what might be its ceiling, as increasing numbers of layers are used?
- Mold Stacking of Alternative Layers
Mold stacking requires tight uniformity and defect control, minimum in-plane displacement and nitride shrinkage, acceptable wafer bowing after thermal stress, and high nitride/oxide wet etch selectivity for patterning accuracy and electrical performance. Increasing the stacking layers increases the chance for defects (since defects are propagated through the upper layers), magnifies device stress (which can bow or warp wafers), and increases process complexity and management. 
- Word-Line (WL) Staircase Definition
Multiple WL lithography steps are currently used, with repeated vertical step etching and 2D trimming at each staircase, to provide the “up and down” shape of the WL staircase used in 3D NAND devices. This series of process steps requires precise etch step profiling, trim etch uniformity and pull-back CD control for the WL contact [3, 4]. As you add more 3D NAND layers at a given cell density, the WL staircase also needs to lengthen and takes more space. For example, in the case of a 32-layer NAND device, the WL staircase stretches out 20um from the edge of the cell array. For a 128-layer architecture, the WL staircase would extend out 80um . Current WL staircase designs may be a key obstacle to cell efficiency and scaling of this type of 3D NAND architecture, due to this linear scaling effect. Alternative solutions are being proposed to address this issue .
- High Aspect Ratio (HAR) Memory Channel Etch
Creating the holes needed by memory channels using extreme HAR etch (with an aspect ratio greater than 40) through 90+ NAND layers challenges the physical limits of current plasma etch technologies. More than a trillion holes need to be etched on every wafer. According to Harmeet Singh at Lam Research, issues include “incomplete etching, bowing, twisting, and CD variation between the top and bottom of the stack. Such defects can lead to shorts, interference between neighboring memory strings, and other performance issues.” . Stacking several decks of memory arrays (e.g. 2 decks of 64-layers to provide an equivalent 128-layer array) may relieve challenges of HAR etch but also impose cost and yield concerns.
- Word-Line (WL) Replacement Gate Fill
Again, according to Harmeet Singh at Lam Research “For replacement-gate schemes, WL tungsten provides the critical conductive links between individual memory cells within layers. This process is particularly challenging because of the need to achieve void-free fill of complex, narrow, lateral structures with minimal stress on the memory stack.”  As Singh also noted, traditional CVD tungsten with high tensile stress can lead to wafer bowing, and fluorine out-diffuse during the process is also known to create yield-limiting defects. A low-fluorine tungsten (LFW) ALD process is a possible current solution . However, tungsten WL thickness requirements (due to resistivity) will limit the thickness that the stack layers (ONON) can be shrunk, resulting in an increasing aspect ratio of the memory hole etch. A new WL metal with low resistivity may be necessary for scaling and increasing the number of layers used in future NAND architectures.
With 3D NAND evolving and the cost-per-bit decreasing below the level of 2D NAND, people expect 3D NAND will continue to support the bit growth of Moore’s Law by expanding memory scaling in a vertical direction. However, if this bit growth relies only on an increase in the total number of layers, processing time per wafer could become cost-prohibitive . If the processing time for a wafer expands excessively, the technology will become untenable. Recently, four-bit-per-cell QLC technology has been announced which provides a 33% capacity boost over three-bit-per-cell 3D NAND . This is one of ways that the industry could relieve capacity growth stress caused by increasing stack height. However, the difficulty of discriminating between 16 possible voltage levels of a QLC memory cell, as compared to the 8 voltage levels of a TLC cell, will impose costs of lower write endurance and performance . It’s doubtful that the industry can keep improving the bit-per-cell number to improve capacity growth, irrespective of the availability of floating gate or charge trapping gate schemes.
In summary, current 3D NAND architecture has several bottlenecks that may limit adding device layers to increase architectural density. This creates challenges and opportunities for innovative integration solutions as well as innovation in single unit process technologies and tool design. Let’s see what the next breakthrough will be!
 Aton Shilov & Billy Tallis , multiple articles from AnandTech, May – July 2018
 Thorsten Lill, “Overcoming Challenges in 3D NAND Volume Manufacturing”, Flash Memory Summit 2017, July 8, 2017
 Harmeet Singh, “Overcoming challenges in 3D NAND volume manufacturing”, Solid State Technology, July 27, 2017
 Jim Hardy, “How Samsung Will Improve 3D NAND Costs”, The Memory Guy, Aug 27, 2017
 Sang-Yung Lee, “What’s Wrong with 3D NAND”, EE Times, June 29, 2017
 Tallis, Billy, “Intel And Micron Launch First QLC NAND: Micron 5210 ION Enterprise SATA SSD”, ANANDTECH, May 21, 2018