Accelerating Semiconductor Module Development using Shared Process Libraries

One of the fastest ways to predict semiconductor manufacturing final results is by adding together the results of performing individual process steps. Unfortunately, this prediction might ignore critical defects that occur in the middle of the combined process sequence. This is the reason that we use advanced computer programs to simulate processes or emulate process integration – to understand accumulated process defects as they occur during the semiconductor manufacturing process.

In SEMulator3D^®, process sequences can be stored and modified in process libraries.  Most engineers have their own process libraries that are customized for personal use,  with many users building their own models and libraries from scratch for each process study.   In this article, we will discuss the benefits of using shared, calibrated process libraries during semiconductor technology exploration.

Using Process Libraries to Model Metal Line Structures

As an example, suppose that a thin-film engineer wants to simulate a back-end metallization scheme and study the feasibility of this scheme and the related module connectivity. The engineer has the ability to simulate each of the metal line processes, and thinks that two possible designs would be feasible.

Figure 1:  Two different metal line connection designs under consideration

In Figure 1, the design on the left (Design A) displays metal lines which are connected sequentially – M1 to M2, and M2 to M3. The design on the right (Design B) displays metal line M1 connected to M3, and metal line M3 connected to M2, along with an additional isolated M1 line.

In Figure 2, a simulated 3D model of the two designs from Figure 1 is displayed.   The engineer will now develop two process sequences to validate each of the 2 metal line designs.

Figure 2:  Simulated 3D Models of the two different metal line connection designs

Using process modeling software, the engineer begins to simulate the desired metal line structures based upon the newly-developed process steps (see Figure 3).

Figure 3: Metal line structures simulated using newly-developed process steps

Unfortunately, the engineer does not know which etch process will be required to create the connecting vias needed by this module.  Vias must be etched to connect together the different levels of metal lines (M1, M2 and M3) used in the module. To develop a successful back-end metallization scheme with fully connected metals, the process model must contain not only the metal line process steps but also the calibrated etch steps (or sequences) that can used to simulate the process of building connecting vias. 

Using shared process libraries to build complete modules

Figure 4: Structure using etch process library developed by an etch engineer

Let’s assume that our thin-film engineer has received an etch process structure and library from an etch engineer (Figure 4).  The etch process library (Figure 4) can then be used to simulate the etch structures and combine them with the engineers’ newly-developed metal line structures.

Figure 5: Design A simulated with both process libraries

Figure 5 displays the simulation results of using Design A, built using a combination of metal line deposition process steps and the contributed etch process library. This design was simulated simply by merging the engineer’s new metal line process library along with the pre-built etch process library.

Figure 6:  Design B simulated with both process libraries.  An unetched via is highlighted

Figure 6 displays the simulation results of using Design B, again built with a combination of metal line processes and etch process steps using the 2 process libraries.   In this case, one via was not etched long  enough, and there is an incomplete etch between the metal layers.  Unfortunately, the merged structures and libraries did not provide the intended result. The engineer will need to modify the via etch processes  using newly calibrated etch steps, and verify that the design is correct .

Process recalibration (modifications) to correct errors found during simulation

Since the engineer didn’t achieve the expected metal connectivity in Design B, the etch process in this design will need to be re-calibrated or the design itself modified.   The etch was not deep enough to connect the M1 and M3 metal layers.   The via etch process will need to be lengthened to increase the depth of the via.  Figure 7 displays how the via connection between the M1 and M3 layers can be corrected by using an etch process that is 3 times longer.

Figure 7:  Design B with calibrated (lengthier) via etch

Alternatively, the metal layers in the vertical dimension can be moved closer (while still using the original, shorter etch process), since there is still a gap between all of the metal lines even if the shorter via etch is used between the M1 and M3 metal layers (Figure 8).

Figure 8:  Design B with modified metal layers

Now that the problems with Design B have been identified, we can simulate the 3 metal line connection structures (one version for Design A, and 2 versions for Design B), using our 2 process libraries and the re-calibrated etch process results (see Figure 9).

Figure 9:  Final simulation results

This process development could have been completed by one engineer, but in this case the thin film engineer did not have a completed etch process library.   In addition, using a 2^nd process library provided access to validated etch process information, which helped to avoid lengthy delays in process development.  It is much more efficient for teams to collaborate and share accurate process libraries, since this leads to higher accuracy simulations and accelerated module development.  Building and sharing sets of process libraries not only increases the process expertise available within a company, but also leads to more accurate process modeling and faster time to market.