By: Sandy Wen, MSEE, Semiconductor Process and Integration Engineer, Coventor

Silicon Photonics Test Die

With the increasing need for faster data transfer rates, the transition from electrical to optical signaling in data processing is inevitable.   Copper cabling cannot keep up with the upcoming data center bandwidth requirements, for applications such as multimedia streaming and high performance computing.  One technology that could enable true optical communication is silicon photonics. Silicon is transparent to IR and is compatible with the 1.3um and 1.55um wavelengths used with fiber optics. While conventional III-V photonics devices are still in demand, silicon for photonics provides the advantage of a low-cost solution that could be integrated with CMOS through conventional silicon processing.

So how are silicon photonics chips manufactured? In most cases, SOI wafers are used.   The high contrast in refractive indices between the silicon and the oxide in the buried layer or the top cladding (oxide or nitride) result in internal reflection. In a typical process flow, the silicon is etched to two depths – one depth to define features such as gratings or ribs, while the other depth etches the entire thickness to the buried oxide for isolating components. Active devices such as modulators or photodetectors are doped to form PN or PIN junctions. Contacts and metallization add electrical connectivity to these active devices, while optical cables are mounted in alignment with couplers such as focusing gratings.

Silicon photonics test die with top cladding removed to show structures, with close-ups of a (a) Mach-Zehnder modulator and (b) directional coupler

Silicon photonics processing may sound simple when compared with the manufacture of state-of-the-art logic devices, but manufacturing challenges abound.   Even Intel, a leader in FinFET manufacturing technology, took sixteen years to develop its first Si photonics product before starting shipments this year.   For example, since film thicknesses are selected for optimal optical transmission, process variations that alter waveguide geometry – like uneven etch depths or angled sidewalls— could result in unwanted birefringence or propagation loss.   Beyond on-chip processing challenges, device packaging could include integration with a light source (laser) and fiber optics, adding a different set of design and manufacturing challenges.   These challenges will need to be addressed by design tools (software, modeling) that can help engineers understand process variability and packaging issues inherent in silicon photonic devices, so that new silicon photonics devices can more quickly reach commercialization.

While current applications of silicon photonics are mostly in the data-center world, there are also increasing demands for high bandwidth in conventional logic and memory and in on-board chips. With silicon photonics now proving to be manufacturable, optical interconnects no longer seem like a pipe dream, and it’s only a matter of a lot of R&D (and time) before the vision of silicon photonics is fully realized.