By: Jimmy Gu, Coventor Technical Staff
One of the top and probably toughest challenges that process integrators are facing today in a silicon fab is process variability. As a former process integrator working hard to ramp up the yield of 22nm FinFET technology, I saw it first-hand. Looking back, I wish I was equipped with the SEMulator3D virtual fabrication platform, which is designed to address this type of process variability challenge. With the recent release of SEMulator3D 5.1, its process variability toolbox has just received a powerful new addition: the ability to model line edge roughness (LER) and line width roughness (LWR) in lithography.
Why is LER and LWR so relevant in state-of-the-art process technology? The continued scaling of transistor and interconnect feature size, and the introduction of 3D structures such as FinFETs and 3D NAND, has brought significant challenges to process control of key structural variation sources such as LER and LWR. These structural variations are typically introduced during a lithography process and carried through subsequent complex process integration schemes. The final end-of-line LER and LWR on the wafer can become yield limiting factors, by increasing transistor threshold voltage variations leading to SRAM read/write fails, or by reducing BEOL process margins causing open/shorts in interconnects. As a result, much effort has been placed on designing robust integration schemes and implementing new process changes to ensure healthy LER/LWR. Therefore, the ability to incorporate realistic LER/LWR modeling in lithography will add an important dimension of process variability that is needed to facilitate a process integrator’s day to day process development work.
As an example, I have recently worked on a test case with the SEMulator3D virtual fabrication platform, to find out how LER and LWR are carried through in a typical BEOL SAQP integration scheme. The goal of this study was to shine some light onto a few interesting questions:
1) How does etch and deposition alter LER on line edges respectively in a SAQP flow?
2) What is the frequency response of etch and deposition effects on LER?
3) What process factors determine the final LWR of the trenches?
4) How can one reduce LER and LWR?
In this work, the initial LER was applied through lithography. Using a random line generation algorithm, noise of characteristic wavelengths and amplitudes were superimposed to form exposure edges with the expected LER. The LER and LWR after each process was measured using advanced virtual metrology. By carefully analyzing the virtual experiment data that was similar to data that might be gathered from a real fab, we’ve discovered a number of interesting results. These results will be disclosed in a 2016 SPIE Advanced Lithography poster entitled “Predicting LER and LWR in SAQP with 3D virtual fabrication” (Paper 9782-22 in the Advanced Etch Technology for Nanopatterning Session). Please come to this informative poster session. I am excited to explain and discuss this work in greater detail !
In the latest release of SEMulator3D 5.1, LER/LWR is fully integrated into our lithography engine by applying random noises on lithography line edges. The noise is characterized by RMS amplitude and correlation length following Fourier Synthesis techniques. Random edge noise can be applied in addition to any other lithography variability parameters such as CD bias and mask shifts, capturing most of the variation sources associated with a lithography process. I believe that the new LER modeling capabilities in SEMulator3D will generate many valuable use cases, helping engineers tackle the toughest process variation challenges.