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Chip packaging has expanded from its conventional definition of providing protection and I/O for a discrete chip, to encompassing a growing number of schemes for interconnecting multiple types of chips. Advanced packaging has become integral to embedding increased functionality into a variety of electronics, such as cellular phones and self-driving vehicles, by supporting high device density in a small footprint. Advances in the chip packaging industry have even caused the IEEE Components, Manufacturing and Technology Society (CPMT) to change its name in 2017 to the Electronics Packaging Society, broadening its initial technical scope [1].
One type of advanced packaging technology is called “wafer level packaging” (WLP), in which an integrated circuit is packaged while still part of the wafer. This type of packaging can create a wafer package that is nearly the same size as the original die. An example of wafer level packaging is the Embedded Wafer Level Ball Grid Array (eWLB), which was originally developed by Infineon in the late 2000’s [2]. Variations of this package type are in use by a number of OSATs today. In this packaging scheme, known good dies are placed face-down on a carrier wafer, then embedded in an epoxy mold. The die-mold combination forms a reconstituted wafer, which is then processed to form redistribution layers (RDLs) with bumps on the exposed die faces for “fan-out” redistribution. The reconstituted wafer is subsequently diced prior to final use (Figure 1).
Figure 1: eWLB processing
Other advanced packaging technologies used in combination with wafer-level packaging are illustrated in Figure 2.
A through silicon via (TSV) is a vertical interconnect that passes entirely through a silicon substrate. In Figure 2, the TSV is depicted within a silicon interposer, where the interposer provides an electrical interface between the high density die and its packaging connections. Initially promoted as an alternative to wire-bonding, TSVs enable multi-die stacking for 3D integration, while optimizing electrical resistance by minimizing interconnection lengths.
RDLs are conductive interconnects that redistribute electrical connections to die pads for I/O; they can be located on one or both sides of a die. To keep up with today’s bandwidth and I/O requirements, RDL line widths and pitch requirements are increasingly shrinking, and are being processed similarly to BEOL (back end of line) connections using copper damascene processing to enable smaller line widths. Likewise, instead of conventional solder bumps, copper pillars are being used to achieve fine-pitch connections between dies.
Figure 2: Example of a device package.
Advanced packaging technology continues to evolve and to support increased device density and I/O connectivity. A recently developed technology, copper hybrid bonding, could circumvent pitch limitations for bumping by direct bonding copper and dielectric on one surface to corresponding regions on another active surface. We eagerly await these new innovations in packaging that will enable the next generation of advanced electronics.
References
[1] IEEE Electronics Packaging Society. https://eps.ieee.org/about/eps-history.html
[2] M. Brunnbauer, E. Fürgut, G. Beer and T. Meyer, “Embedded wafer level ball grid array (eWLB),” 2006 8th Electronics Packaging Technology Conference, Singapore, 2006, pp. 1-5, doi: 10.1109/EPTC.2006.342681.
