Driven by Moore’s law, memory and logic semiconductor manufacturers pursue higher transistor density to improve product cost and performance . In NAND Flash technologies, this has led to the market dominance of 3D structures instead of 2D planar devices. Device density can be linearly increased by increasing stack layer counts in a 3D NAND device . At the same time, patterning scheme optimization can also enhance 3D NAND effective device density. In this discussion, we will analyze various patterning schemes for staircase and slit structures at different TCAT (Terabit Cell Array Transistor) 3D NAND nodes. We will compare these schemes to understand their impact on effective transistor density. The schemes and data used in this study are based upon (or inferred from) tear down reports published by TechInsights®. Variations in patterning schemes, and the resulting virtual structures, were modeled using the SEMulator3D® semiconductor platform.
In 3D NAND, slit pitch in the bitline direction, and stair pitch in the cross bitline direction, are two of the most important factors in determining memory cell and staircase area. Traditionally, memory cell and staircase area could be reduced by decreasing the CD and pitch of the slit and stair structures. Unfortunately, these changes can introduce many challenges in lithography and downstream etch and gap filling processes. For example, if the slit pitch is reduced, the channel hole pitch must also be decreased at the same time. With a smaller channel hole pitch and CD, the allowed process window for other processes (such as the channel hole to channel hole bridge during the etch process, or the channel hole to substrate open in both the etch and deposition processes) will become narrower. Also, shrinking the stair CD and pitch will require a more uniform stair angle along with a much smaller CD variation in the stair etch process. These narrower process windows are needed so that the downstream stair contact will precisely land on the staircase center without shorting the word line at the stair sidewall. Enhancing device density without sacrificing the allowed process window is a key issue in 3D NAND process development.
To explore this issue further, 32P, 64P and 96P TCAT 3D NAND devices were modeled using reverse engineering reports from TechInsight. Figure 1 displays a top view of 3D NAND slit and channel holes at the 32P, 64P and 96P nodes, while Figure 2 presents a cross-sectional view of a 3D NAND staircase at these same nodes. Basic dimensional information about the modeled structures are summarized in Table 1. In Table 1, slit and stair pitch are not reduced at the more advanced nodes. On the contrary, they were enlarged to broaden the process window. The channel hole counts per slit, along with wordline pair counts per stair, are increased at the two most advanced nodes. We will discuss how to enhance memory density without shrinking the absolute pitch and CDs, by changing the patterning scheme.
At the 32P TCAT process node, 1 of 4 memory cells can be exclusively addressed between any two slits using a combination of bitlines and wordlines. At the 64P and 96P process nodes, an extra mini slit process is introduced to cut the center dummy channel hole and effectively split 9 holes into 4 holes on each side. The mini slit divides the top 3 ON stacks into 2 sides, with the left and right sides connected to separate string select lines. With the combination of bit lines, word lines and string select lines, 1 of 9 memory cells can be exclusively addressed using the mini slit and two larger normal slits. The introduction of a mini slit provides three benefits:
Unfortunately, these benefits have an extra cost in additional processes and masks. Furthermore, the replacement metal gate process is much more challenging, due to a larger lateral etch and deposition distance.
Figure 3 displays the mini slit layout design (Figure 3a), with a cross-sectional and top view of the TCAT mini slit. Figure 4 highlights the mini slit process flow modeled in SEMulator3D. The process flow consists of two steps, comprised of mini slit lithography and etch processes after ON stack formation, followed by mini slit and stair oxide filling processes after the staircase etch.
In 3D NAND, wordline metal is connected to BEOL metal through the stair contact in the staircase area. Each wordline metal layer is also split at each staircase. In the 32P TCAT process (see Fig. 2), each wordline metal was assigned to a single step in the cross bitline direction. In the 64P and 96P processes, each staircase includes 4 pairs of wordline metal in the cross bitline direction, highlighting that extra mask and process steps are necessary to split these 4 stacks from a single stack in the bit line direction. Traditionally, to split 4 stacks from a single stack, 2 masks would be necessary. Lithography using thick resists and trim step etching have been widely adopted in staircase formation. Therefore, it is possible to use a split mask combined with a trim process to split 4 stacks from a single stack before the main staircase etch process.
Figure 5 displays a potential split and stair layout design using a 64P process. We assume that the bitline is oriented in the Y direction while the wordline is oriented in the X direction. The stair stack split step is designed to split ON pairs into 4 different depths in the right and left side of the cell area. The depth should be complementary on any two sides containing the same Y coordinate, so that a particular wordline can be selected on a particular side.
Figure 6 provides a 3D visualization of the process steps used in the stair stack split. In the stair stack split, 1 split mask, 3 etch steps and 2 trim steps are necessary as illustrated in Figure 6. Before each etch step, the resist boundary in the Y direction should strictly align with the slit or mini slit through use of either lithography or a resist trim process (the larger slit downstream should align on the resist boundary). Thus, each trim step will consume about 740nm of resist in both the X and Y directions. Figure 7 highlights the stair profile at the cell edge of an actual chip, displaying a similar profile to the Cut1 image in Figure 6 and demonstrating the accuracy of the process model.
Figure 8 illustrates the main staircase formation process after completion of the split process. In this illustration, 3 stair masks, 3 lithography steps and 7 etch steps are combined with 6 trim process steps (after each lithography step) to form more than 16 staircase structures. 4 pairs of ON stacks are removed at each etch step. About 670 nm of resist is consumed at the sidewall during each trim step. If you compare the cross section Cut1 image in Figure 8 with the actual chip image in Figure 5(c), a very similar staircase profile is shown. It should be mentioned that in these processes, the stair mask sequence could be modified from stair 1->2->3 to 3->2->1. This staircase patterning scheme may provide multiple benefits. Area could be saved in the X direction by using a split mask to split 4 stacks from 1 stack in the Y direction, creating 4 pairs of ON stacks. In addition, fewer masks may be needed in the X direction.
In this study, we have used SEMulator3D to create process models of 3D NAND split and staircase patterning schemes. The SEMulator3D virtual fabrication platform provided increased understanding and visibility into these complex 3D NAND integration schemes and their resulting 3D structures, along with a time and cost-efficient optimization methodology.