This blog is a summary of a technical paper given at an SPIE Photonics conference. Read the full paper here.
Silicon photonics is an emerging and rapidly-expanding design platform that promises to enable higher-bandwidth communication and other applications. One of the best qualities of silicon photonics is its ability to leverage existing CMOS fabrication equipment and process flows. However, this means that it is subject to the same process defects and variations. Previous blog posts [References 1,2] have detailed the power of utilizing process simulation to explore the impact of fabrication defects on photonic integrated circuit (PIC) component performance.
Design for manufacturability (DFM) models for silicon photonics are not as mature as their CMOS counterparts. However, it is possible to use virtual fabrication and optical simulation experiments to capture worst-case scenarios for a given device and process defect. This can help answer the question, “Given a window of fabrication variability, what is the worst-case scenario on device performance for a silicon photonic device?” We will explore the effect of a common manufacturing defect that occurs during lithography and etch processing, known as line edge roughness (LER), on photonic (PIC) device performance. In this study, we will analyze the effect of LER on a Y-branch splitter [Reference 3] using semiconductor process modeling (virtual fabrication) and optical simulation. The results being presented are a subset of results obtained during a joint collaborative effort between Coventor and Professor Duane Boning’s group at MIT. Additional detail regarding this study can be found in Reference .
Silicon-on-insulator (SOI) waveguides have dimensions that are carefully designed to guide modes (most often the fundamental TE mode) with minimal leakage into the surrounding cladding materials (usually SiO2). These modes are normally supported at a free-space wavelength of 1550 nm, a common telecommunication wavelength. When LER exists on the waveguide sidewalls, it acts as a small perturbation to the width, resulting in propagation loss [see Reference 1]. The perturbation amplitudes are small (the worst case tends to be around 15 nm, which is 3% of the usual total waveguide width of 500 nm), but nonetheless these perturbations interact with the traveling mode and cause non-ideal device behavior.
In our work, the device under study is a Y-branch splitter, as shown in Figure 1:
Light is injected into the single input port shown at the top of the figure, split at the junction region into two streams (each containing 50% of the input intensity in the ideal case), and measured at the two output ports (the “upper” and “lower” ports). Y-branch splitters are one of the most common PIC elements. For example, two Y-branch splitters are used to form the two ends of a Mach-Zehnder Interferometer (MZI) [Reference 3]. A Mach-Zehnder Interferometer splits an input beam into two parts at one end, propagates the light in two arms (possibly developing a relative phase shift between the two streams), and recombines the light at the other end via a Y-branch which is used as a combiner. Due to the need for accurate MZI measurement results, LER should not significantly impact the transmission characteristics of light propagation through the waveguides used in the device.
To analyze the impact of LER on Y-branch transmission, we ran combined virtual fabrication and optical simulation models on a Y-branch structure. Since LER is a stochastic process that causes random width fluctuations on the device sidewalls, we executed many simulation events containing unique random noise profiles to capture the expected variance in output transmission power. The Y-branches were virtually fabricated in SEMulator3D®. Random noise was generated using a Gaussian autocorrelation function described by two variables: the root mean square amplitude (RMSA) and correlation length (CL). The RMSA describes the average amplitude deviation from the nominal (flat) sidewall surface, and the CL describes the spatial length scale over which the noise is correlated. Small CL’s retain more high-spatial-frequency components, leading to more oscillations per unit length, and the converse is true for large CL’s. Several different RMSA/CL combinations were chosen in our study, to span a window of observed values reported in the literature.
After the structures were virtually fabricated in SEMulator3D, they were then exported via SEMulator3D’s surface mesh generation step and imported into Lumerical® FDTD software [Reference 5] for optical simulation. In Lumerical, the power at each output was measured for every unique combination of RMSA and CL.
The defining characteristic of a Y-branch is that it splits light intensity equally between two output ports. However, LER causes the transmission to become imbalanced.
In Figure 2, the transmission imbalance (defined as the difference in relative output power between the upper and lower ports) is only a few percent over all wavelengths and is dependent upon the RMSA and CL of the sidewall noise. Figure 3 plots the maximum imbalance observed over 50 simulation runs, using several combinations of RMSA and CL values at a wavelength of 1550 nm.
Figure 3 shows that increasing both RMSA and CL increases the maximum imbalance observed in each case, leading to a worst-case imbalance of ~15% when RMSA=15 nm and CL=60 nm. The average imbalance from 50 simulation runs (over all wavelengths) was only a few percentage points or less, but in the worst-case scenario a given Y-branch can be significantly impacted by LER.
Another adverse effect of LER is excess loss, defined as the sum of the powers of the upper and lower ports divided by the input power. Again, the worst case occurred in our study when RMSA=15 nm and CL=60 nm (at a wavelength of 1550 nm), as shown in Figure 4.
All 50 simulation runs had excess losses greater than the nominal case (with loss due to radiation at the junction region [ Reference 6]) and approached -0.8 dB (~17%) in a worst-case scenario.
PIC component designers can leverage the power of virtual fabrication and optical simulation to analyze worst-case corner scenarios for their devices. From studies like these, compact models can be created and inserted into a circuit model to better understand the impact of PIC process variation on overall circuit performance.
If you wish to learn more about this study, please click here to download the original published paper.