BEOL Patterning Comes to the Forefront

I just got back from the annual International Electron Devices Meeting (IEDM) in Washington, DC. As is customary, a great deal of attention was paid to Front End of Line (FEOL) transistor innovations such as FinFET, FDSOI, Graphene, Nanotubes, Nanowires, etc. However, some of the greatest complexity in semiconductor development and manufacturing these days is in the interconnect, or Back End of Line (BEOL). The BEOL contains some of the finest geometries in the technology, since die area scaling is usually limited by the wiring density. Because wires are being designed at such fine dimensions, their height has been increased to recoup the resistance penalty. This makes the dimensions even more challenging through high aspect ratios. Finally, the BEOL contains some of the most complex and unstable materials due to the desire to reduce capacitance (porous low-K dielectrics), the requirement to minimize thermal cycles (for FEOL stability), and the inherent reliability risks associated with the metals involved. I’ve been a transistor specialist for most of my career, but I have to admit… the BEOL has gotten incredibly difficult.

BEOL Integration effectively breaks down into two parts: patterning and metallization. Most FEOL bigots refer to this cycle as “Drill, Fill, and Repeat”. Metallization has an amazing amount of complexity, but that’s a story for another day. BEOL patterning is incredibly complicated in advanced technology nodes for one primary reason: we’ve been scaling these dimensions for five technology nodes (45/40nm, 32/28nm, 22/20nm, 14nm, 10nm) on a single lithography platform, the 193nm immersion system. EUV has been promised for generations, but still isn’t ready for primetime. Yet, the technology scaling march has continued. A few different patterning and integration schemes have emerged to enable dimensions well beyond those intended for the current state-of-the-art in lithography. These BEOL patterning schemes, as well as some analysis of their challenges, are presented in an article on Tech Design Forum.

The technical challenges for these new technologies are pretty clear. However, the potentially bigger problem for the remaining companies who dare develop advanced technologies is the cost and schedule of developing these process flows. Each level of the BEOL now requires double the lithography passes as previous nodes, with many more processes, additional measurements, new inspections and novel defect mechanisms. To conduct this development on the same schedule requires doubling fab throughput or doubling development resource allocation. This can’t be the smartest way to proceed! Advanced process modeling, such as SEMulator3D virtual fabrication, offers the capability to run many virtual wafer experiments in parallel with the physical wafer experiments in the fab. These virtual wafers deliver much the same data as the physical wafers, at a dramatically reduced cost and a throughput that is only limited by the computational horsepower allocated (much faster than a fab!). Deploying virtual fabrication in a technology development organization is the lowest cost method for increasing the experimental resource. Teams that try to do technology development the old fashioned way, with more wafers and higher fab throughput, will soon be left behind by the teams that intelligently expand their experimental capability with advanced modeling tools like SEMulator3D virtual fabrication.

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