Controlling Variability using Semiconductor Process Window Optimization

To ensure success in semiconductor technology development, process engineers must set the allowed ranges for wafer process parameters. Variability must be controlled, so that final fabricated devices meet required specifications. These specifications include critical dimensions, electrical performance requirements, and other device characteristics. Pre-production or ramp-up production Si wafers, which are processed in the fab but not yet optimized, are the usual source of test data needed to understand and control this variability.

Cross-correlation and analysis of thousands of test data points is often required to optimize and calibrate process parameters and meet device specifications. Gathering this necessary data using non-optimized, pre-production wafers is very costly. Reducing the number of pre-production test wafers required to set the optimal process parameter ranges (known as the “process window”) will dramatically reduce the cost and risk of semiconductor technology development.

Addressing the Challenge of Process Optimization

Coventor, a LAM Research Company, is addressing this challenge with the introduction of a new feature in SEMulator3D^® called Process Window Optimization (PWO). This feature expands the Analytics capabilities of SEMulator3D, providing an automated method for process window optimization. PWO can substantially reduce the number of pre-production test wafers needed to meet final device specifications. More importantly, it can accurately predict maximum success rates achievable for existing processes under consideration.

Process Window Optimization

Process Window Optimization in SEMulator3D follows a structured methodology. First, a user builds and calibrates a virtual model of their device technology (a “digital twin” wafer). Virtual metrology steps are set in the model to measure selected fabrication/device parameters, just like performing real physical metrology on test wafers. The virtual metrology steps can be used to monitor compliance with device specifications. A specification (min/max values) for each of the metrology steps must then be provided for the Analytics studies. For each chosen process parameter, a process window is also established. Nominal values of the process parameters (such as the target value and allowed variability measured by standard deviation) are set according to the capabilities of the fab where the device will be manufactured.

Next, a user executes a virtual Design of Experiments (DOE) corresponding to a set of experiments performed on physical wafers. The experiment must include a defined search space for each of the selected parameters. To obtain statistical significance, the simulated experiment is run many times across the user-defined parameter space. The Process Window Optimization algorithm then provides an optimized value for each process parameter, maximizing the percentage of the selected fabrication/device parameters that meet their metrology specifications (“in-spec percentage” or “inSpec%). This part of the workflow is shown in Figure 1.

Once calculations are complete, the target and standard deviation values of each process parameter can be modified by the user, to understand the direct impact of these modifications on the metrology in-spec percentage (see Figure 2).

An Example of PWO using SAQP Patterning

This methodology will be illustrated using a prior model discussed in a published report entitled “Improving SAQP Patterning Yield using Virtual Fabrication and Advanced Process Control”. In our current PWO study, patterned lines and spacing were measured by virtual metrology and were all targeted at 16nm with a success criterion of +/-10%. We only varied two parameters in this study: the thicknesses of spacer 1 and spacer 2. Spacer 1 and Spacer 2 nominal targets were set at 13.5 nm and 18.8nm, respectively, with the same standard deviation of 0.2nm. The search spaces were defined for those two parameters as 11.7nm to 15.3nm and 17nm to 20.6nm, respectively. A total of 1000 runs were executed.

Figure 3 displays a graph containing all process parameter combinations considered in the DOE (with each point representing one run). The blue points represent runs which fulfilled the success criterion of having all metrology measurements at 16nm +/-10%.

As shown in Figure 4, assuming a 0.2nm standard deviation for spacer 1 and spacer 2 thicknesses, the PWO system reported an increase in metrology in-specification percentage from 69.6 to 74.6% (maximized) when changing the spacer 1 nominal value from 13.5nm to 13.4nm and spacer 2 nominal from 18.8nm to 18.9nm. Moreover, reducing the spacer thickness standard deviation from 0.2nm to 0.18nm increased the metrology in-specification percentage to 85.1%.

Conclusion

This simple example (with only two parameters considered) was chosen for ease of illustration using a 2D representation (Figure 3). This methodology, however, can easily be extended for much more complex cases. For example, device technology co-optimization (DTCO) for multiple and interdependent process steps can be analyzed using PWO to perform more complex technology yield optimization.

In conclusion, the new SEMulator3D PWO technology offers several key insights. It can:

1. Accurately predict a maximum success rate achievable for existing process (fab) capabilities
2. Determine the nominal process conditions required to achieve a maximum success rate
3. Define the process variation control improvements required to increase the success rate of a semiconductor process to a specific target

PWO is highly time and cost-effective, since the DOE only requires a limited number of processed Si wafers for virtual model calibration and can be used well in advance of volume production. This contrasts with fab-based testing, which requires a substantial number of processed Si wafers and poses a high risk to device commercialization timelines. The PWO capabilities in SEMulator3D can accurately predict the outcomes for existing processes under consideration, and substantially reduce semiconductor technology development timelines and risk.