Defect Evolution in 3D NAND Flash

by Sandy Wen, Semiconductor Process and Integration

3D NAND Flash has become a hot topic in non-volatile memory these days. While planar NAND flash is still going strong, it has been increasingly difficult to scale planar technology past the sub-20nm lengths and meet upcoming memory cell density and cost targets. In a different approach, Toshiba published early work on 3D NAND in 2007 [1] in which flash cells are stacked vertically to increase cell density. Since then, all major flash memory manufacturers have jumped aboard this train with their own flash architectures, and in 2013, Samsung became the first to ship “V-NAND” in the form of a solid state drive.

Figure 1. Example of a 3D NAND flash memory array.

Figure 1. Example of a 3D NAND flash memory array.

While 3D NAND flash development is in full-swing, manufacturing these vertically-oriented memory strings is extremely challenging. We’ve previously blogged about issues in 3D NAND process integration; this time around, we explored defect evolution during 3D NAND flash processing using SEMulator3D to virtually fabricate the device while placing defect particles in various locations.

The deposition of multi-material film stacks used to create cell strings requires additional defect control. If a defect or other particle becomes embedded in the bottom of these films stacks, the above layers can be deformed so that the resulting surface topology is no longer flat. Obviously, the defect can directly block the channel etch and prevent the NAND string’s channel from reaching the ground (Figure 2a). What is less apparent is the channel etch behavior when the defect is not necessarily in the path of a cell string: the resulting surface deformation can affect the channel etch or wordline cuts, and cause other nearby strings to etch improperly, resulting in cell failure (Figure 2b). Consequently, various process equipment vendors have worked hard to improve film deposition through defect reduction and adjusting film smoothness.

Figure 2. (a) Defect blocks one channel from etching to completion. (b) Defect causes underetch of two

Figure 2. (a) Defect blocks one channel from etching to completion. (b) Defect causes underetch of two

Meanwhile, gate fill regions can also be adversely affected by defects. For example, in the TCAT version of 3D NAND flash [2], silicon nitride layers are removed typically with a wet etch, then the resulting regions are filled with a high-k/metal gate stack. However, if defects reside in the overhang region after the wet etch, it can interfere with the gate stack fill. Using SEMulator3D, we placed a defect between the remaining oxide layers after nitride removal (Figure 3a), then continued with the downstream processing. In one case, the defect actually results in an open within a wordline (Figure 3b).

Figure 3. (a) A particle is placed after silicon nitride removal using wet etching. (b) The metal gate deposition is blocked in the region of particle, creating an electrical break in the wordline.

Figure 3. (a) A particle is placed after silicon nitride removal using wet etching. (b) The metal gate deposition is blocked in the region of particle, creating an electrical break in the wordline.

The use of SEMulator3D allows us to evaluate defect evolution in complex structures like 3D NAND flash. These results can help engineers discover potential weaknesses in a nominal process flow, or help them pinpoint various types of defect-based device failures. With these virtual fabrication techniques, cycles of learning can be saved, reducing time to market for 3D NAND flash.

References
[1] H. Tanaka and et al., “Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory,” in 2007 Symposium on VLSI Technology Digest of Technical Papers, 2007.

[2] J. Jang et al, “Vertical cell array using TCAT(Terabit Cell Array Transistor) technology for ultra high density NAND flash memory,” in 2009 Symposium on VLSI Technology Digest of Technical Papers, 2009.

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