Reducing BEOL Parasitic Capacitance using Air Gaps
October 18, 2017
What the Experts Think: Delivering the Next 5 Years of Semiconductor Technology
December 19, 2017
New, advanced semiconductor processing and architectural technologies take years to perfect and put into production. In the meantime, semiconductor customers continue to demand faster, smaller and higher functioning devices. Semiconductor manufacturers need to decide whether (and when) to jump to the next generation of devices and production technologies, weighing the risk and benefit of bringing the next processing and architecture technologies to market.
A recent example of this type of risk analysis can be found in the gradual plans by foundries to adopt EUV technology. EUV technologies will reduce current requirements for multi patterning and (eventually) improve yields. However, EUV technology has many technological hurdles, including mask defects, CD uniformity, and production rate and yield issues. Billions of dollars have been invested in EUV development, yet no foundry is currently using the technology in production.
Could we extend existing technology concepts to deliver the next generations of semiconductor scaling, and avoid or defer the risk of jumping to next generation device and production technologies? Or, does the industry need paradigm-shifting technologies to reach these goals? Is there a way that we squeeze additional angstroms out of existing process and technology elements? Can we use variation reduction and process control to create the next few generations of semiconductor scaling? Or, do we simply need entirely new processes and architectures to reach these difficult goals?
There might be an entire node of scaling available from variation reduction, with numerous opportunities for variation reduction in advanced technology development. Our ability to detect, measure and characterize variability issues will be critical in variation reduction, along with process optimization and co-optimization strategies and challenges. Process controls are a key factor in being able to reduce process variability and to scale effectively.
If you are interested in exploring this topic further, we invite you to attend a complimentary seminar sponsored by Coventor in San Francisco on December 5, 2017, entitled “Everything is Under Control: Delivering the Next 5 Years of Semiconductor Technology”. The seminar will be moderated by Ed Sperling, Editor in Chief of Semiconductor Engineering. Leading semiconductor industry panelists will discuss alternative methods to solve fundamental problems of technology scaling, and review techniques and strategies that might extend the lifetime of the latest technologies and propel us into the future. They will explore the latest advances in semiconductor architectures, patterning, metrology, advanced process control, co-optimization and integration. If you are unable to attend the seminar, keep your eye on future issues of Semiconductor Engineering to view a summary of the discussion.
To pre-register for the complimentary panel discussion, click here.
![Fig. 2. Silicon spin qubit centered in the dotted circle, control and readout signals (M, P, R, T, and Q) are shown in the inset. Simplified schematics of the quantum point contact and corollary circuits are shown. The voltage source is implemented as a digital-to-analog converter at room temperature. (Taken from [6])](https://www.coventor.com/wp-content/uploads/2022/05/Fig.-2.-Silicon-spin-qubit-centered-in-the-dotted-circle-control-and-readout.png)
![Figure 2: Schematic view of standard CMOS including an electro-mechanical switch monolithically integrated into BEOL [2]. Courtesy: University of California, Berkeley](https://www.coventor.com/wp-content/uploads/2022/04/Figure-2-April-2022-MEMS-Blog-for-Coventor-website.png)
