CMP (Chemical mechanical planarization) is required during semiconductor processing of many memory and logic devices. CMP is used to create planar surfaces and achieve uniform layer thickness during semiconductor manufacturing, and to optimize the device topology prior to the next processing step. Unfortunately, the surface of a semiconductor device is not uniform after CMP, due to different removal rates during this process. Factors such as the CMP slurry, pressure, abrasives and other CMP variables during planarization can contribute to non-uniform surface removal rates. These variations in CMP removal rate can cause dishing and erosion defects. CMP can create diverse and unexpected topologies in patterned wafers with different layout densities, not only locally but globally across the entire wafer.
Among all CMP processes in memory and logic devices, metallic CMP in BEOL (Back End of Line) semiconductor processing is becoming increasingly important. CMP erosion and dishing defects due to differences in pattern density are becoming a significant issue, as metal line pitch and width are decreasing. These dishing and erosion defects can cause yield losses and reliability issues in the BEOL structure .
Figure 1 schematically illustrates a conventional metal CMP process in the BEOL portion of a semiconductor device. Metal is deposited on the device after a dielectric etch step. The etch step utilizes a damascene process for M2 and Via formation. Afterward, chemical mechanical planarization occurs. In the CMP process, the main metal is polished at a high removal rate, until the barrier metal is exposed. Next, the barrier metal is removed up to the dielectric layer. Finally, at the overpolish step, the metal and dielectric layers are polished to remove any metal residues remaining across the wafer.
Unfortunately, during the overpolish process, erosion and dishing can occur. Dielectric erosion can be affected by metal pattern density and dishing can be impacted by pattern/trench width . Figure 2(a) displays an example of erosion and dishing after CMP. Erosion can be seen in the densely patterned area on the right side of the diagram, while dishing is shown on the left. This dielectric erosion and dishing can lead to via contact issues. In Figure 2(b), the SiN block is not fully etched during the dielectric etch step, with the etch process stopping before the via can reach the M1 metal layer due to the intervening SiN layer in the dense M1 portion of the device (right). This incomplete etch process can create a High Resistance (HR) defect between M1 and the via, leading to RC delay and performance issues. M1 erosion can also cause metal residues to remain during the M2 metal overpolish step (See Figure 2(c)), depending upon the M1 pattern density and its effect on the rate of erosion.
Engineers can use SEMulator3D® process simulation to analyze CMP defects, including erosion and dishing caused by pattern density variations. The CMP process models can be calibrated with actual wafer data and subsequently simulated in SEMulator3D, at different pattern densities. In Figure 3, the results of a CMP simulation model are shown across different layout densities with the same line width design. A graph of the erosion amount as a function of layout density demonstrates that the erosion thickness increases as layout density increases in the simulation.
As shown in the Figure 4, via resistance increases as M1 pattern density increases due to a decrease in contact area between M1 and the via. M1 resistance in dense areas also increases as pattern density increases due to the lower height of M1, but M1 resistance in the isolated (Iso) area does not change. If the upper spec of the via and M1 resistance is set to 40Ω/um and 50Ω/um respectively, an engineer would need to specify that a maximum 40% M1 pattern density is acceptable (see the Spec Limit red line in Figures 4(a) and 4(b)).
Unfortunately, choosing a 40% maximum pattern density could be an incorrect decision if it was based solely on data related to M1 and Via resistance. There can also be metal residue defects after the M2 CMP process is completed, and pattern density will affect the amount of post-CMP metal residue and subsequent defects (as mentioned earlier). In Figure 5a, metal residue defects (electrical shorts across the M2 lines) become apparent when the pattern density is increased from 35% to 40%. In SEMulator3D, a short defect is measured by extracting resistance or counting the number of separate (non-shorted) M2 metal lines. In this example, we looked at the number of non-shorted metal lines to check for short defects. The simulation indicates that there are no shorts at a 35% pattern density, but the number of shorts increases from 0 to 1 when pattern density is 40% or greater, due to M2 metal residue defects (Figure 5b). The CMP overpolish step can be increased to remove additional M2 metal residue during the M2 CMP process, but it will also reduce the M2 height and increase the M2 resistance. As seen in Figure 6, the second predicted short defect can be removed at 40% pattern density using an additional 3nm overpolish (compared to the Process of Record). Unfortunately, this additional 3 nm CMP overpolish will create unacceptable M2 resistance (above the 40 ohms/um budget), and is not advised.
In this case, the correct design decision is to limit the pattern density to 35%, when we consider all simulation data related to CMP erosion, dishing, resistance and the current CMP process capabilities. Based upon this study, BEOL yield and reliability could be improved by optimizing design rules to restrict the local metal pattern density, and by implementing CMP process improvements to reduce metal erosion in areas of high pattern density.
 M. Gupta et al., “Planarization yield limiters for wafer-scale 3D ICs,” in IEEE/SEMI Advanced Semiconductor Manufacturing Conf. and Workshop, May 2002, pp. 278–283
 Luo, J.; Dornfeld, D. Integrated Modeling of Chemical Mechanical Planarization for Sub-Micron IC Fabrication; Springer: Berlin/Heidelberg, Germany, 2004.