• Skip to main content
  • LOG IN
  • REGISTER
Coventor_New_LogoCoventor_New_LogoCoventor_New_LogoCoventor_New_Logo
  • COMPANY
    • ABOUT
    • CAREERS
    • PRESS RELEASE
    • PRESS COVERAGE
    • EVENTS
  • PRODUCTS
    • SEMulator3D®
      Semiconductor Process Modeling
    • CoventorMP®
      MEMS Design Automation
      • CoventorWare®
      • MEMS+®
  • SOLUTIONS
    • SEMICONDUCTOR SOLUTIONS
    • MEMS SOLUTIONS
  • RESOURCES
    • CASE STUDIES
    • BLOG
    • VIDEOS
  • CONTACT
  • SUPPORT
Contact Us
✕
  • Home
  • Coventor Blog
  • Evaluating the Impact of STI Recess Profile Control on Advanced FinFET Device Performance Using Virtual Fabrication
Figure 2: A test structure designed to calculate capacitance using 2 nets. The 2 separate nets have 6 ports (P1-P6) and 4 ports (P7-P10), respectively.
Performing High Accuracy Capacitance Analysis using SEMulator3D
August 19, 2021
Announcing CoventorMP 2.0
September 17, 2021

Evaluating the Impact of STI Recess Profile Control on Advanced FinFET Device Performance Using Virtual Fabrication

Published by Yu De Chen at September 14, 2021
Categories
  • Coventor Blog
Tags
  • FinFET
  • Process Window Optimization
  • SEMulator3D
Fig. 3: Leakage current distribution from different directions.

Fig. 3: Leakage current distribution from different directions.

Profile variation is one of the most important problems during semiconductor device manufacturing and scaling.  These variations can degrade both chip yield and device performance.   Virtual fabrication can be used to study profile variation in a very effective and economical manner, and avoid process cycle time and wafer cost in the fab. In this short article, we will review the impact of STI (shallow trench isolation) profile on device performance in a 5 nm FinFET vehicle, and demonstrate how SEMulator3D® virtual fabrication can help address profile variation issues[1].

In our study, an SRAM111 architecture was selected as the test structure. Using a combination of fin height and pattern dependence variation in a virtual split experiment, we analyzed the effect of STI footing/trenching, fin height imbalance and fin height profiles using SEMulator3D (See Fig. 1) [2].

Fig. 1: Final STI recess profile

Fig. 1: Final STI recess profile

To evaluate the impact of the STI recess profile on device performance, an NMOS structure was cropped out of the SRAM and used in electrical performance modeling. During STI recess, different STI recess profile geometries were generated for testing. Figure 2 reveals the off-state leakage status across a selected drain voltage sweep range for different geometries. Larger footings and lower fin heights exhibited much higher off-state leakage and slightly lower on-current. These problems were not as large during changes in fin height imbalance. From the leakage curve, it is obvious that higher leakage is caused by increased DIBL (drain-induced barrier lowering) effects seen with lower fin heights and larger footings. The leakage current distribution was also visualized across cross-section profiles using SEMulator3D (see Figure 3). The main contributing factor to leakage current appeared to be source drain punch through at the fin bottom.

Fig 2.: Drain leakage with drain voltage sweep.

Fig 2.: Drain leakage with drain voltage sweep.

 

Fig. 3: Leakage current distribution from different directions.

Fig. 3: Leakage current distribution from different directions.

Based upon these results, we can see that both STI footing issues and imbalanced fin heights can lead to diminished gate control at the fin bottom, similar to the issues seen at a lower fin height. To overcome this problem, an optimal trenching STI profile can be designed which can both boost on-current conditions and lower off-leakage current.

These results demonstrate that rigorous STI profile control may be required to meet performance specifications in an advanced FinFET process setting.

Interested in learning more?

Download the full whitepaper “Evaluating the Impact of STI Recess Profile Control on Advanced FinFET Device Performance” to learn more.

Download Full Paper

 

References

  • https://www.coventor.com/products/semulator3d
  • Fried D et al, SISPAD 2014 Sep 9 (pp. 209-212).
Share
Yu De Chen
Yu De Chen
Yu De Chen is a member of the semiconductor process and integration (SPI) team at Coventor. Yu De worked at TSMC from 2012 to 2014 as a CVD and epitaxy engineer responsible for 16nm and 20nm epitaxy process implementation. In 2014, he joined UMC in Taiwan, working as an Senior OPC Engineer in patterning and design-technology co-optimization for advanced nodes. Yu De joined Coventor in July 2017, and is currently working for Coventor’s SPI group in Taiwan, performing semiconductor process development and applications engineering. Yu De received his Master’s Degree from the Institute of Applied Mechanics at the National Taiwan University in Taipei City, Taiwan.

Related posts

Picture of a young man using virtual reality glasses from the 2018 movie “Ready Player One” from Warner Bros.

An Explanation of the Metaverse and 5 MEMS Technologies Solutions That Will Soon Help Make It Happen

January 18, 2023

An Explanation of the Metaverse and 5 MEMS Technologies Solutions That Will Soon Help Make It Happen


Read more - An Explanation of the Metaverse and 5 MEMS Technologies Solutions That Will Soon Help Make It Happen
Figure 4 displays a single image showing how surface roughness can get transferred to materials etched or deposited later. In this image, the surface roughness has led to scumming, which in turn caused lines to get shorted. The figure shows uneven lines due to surface roughness, with material left behind that crosses two of the lines and creates a short.

Figure 4: Surface roughness can get transferred to materials etched or deposited later. Here, the surface roughness has led to scumming, which in turn caused lines to get shorted.

January 13, 2023

Modeling of Line and Surface Roughness in Semiconductor Processing


Read more - Modeling of Line and Surface Roughness in Semiconductor Processing
Figure 2. Backside power delivery using buried power rails, based on [2] (not to scale).

Figure 2. Backside power delivery using buried power rails, based on [2] (not to scale).

December 19, 2022

The Other Side of the Wafer: The Latest Developments in Backside Power Delivery


Read more - The Other Side of the Wafer: The Latest Developments in Backside Power Delivery
Figure 1:   3D Gyroscope Model example with simulated pressure contours (left), and ambient cavity pressure vs. Q-factor graph with simulated and measured results (right) (courtesy: Murata)

Figure 1:   3D Gyroscope Model example with simulated pressure contours (left), and ambient cavity pressure vs. Q-factor graph with simulated and measured results (right) (courtesy: Murata)

November 28, 2022

Understanding Q-Factors in Gas Encapsulated MEMS Inertial Sensors


Read more - Understanding Q-Factors in Gas Encapsulated MEMS Inertial Sensors

Comments are closed.

Product Information

  • Product Offerings
  • Technical Support & Training
  • Licensing
  • System Requirements

Resources

  • Blog
  • Case Studies
  • Videos
  • 2018 MEMS Design Contest

Company

  • About
  • Press
  • Partners & Programs
  • Contact
© Copyright Coventor Inc., A Lam Research Company, All Rights Reserved
Privacy Policy • Terms of Use
Contact Us
  • LOG IN
  • REGISTER