How FinFET Device Performance is Affected by Epitaxial Process Variations

By: Jacky Huang and Yu De Chen

As the need to scale transistors to ever-smaller sizes continues to press on technology designers, the impact of parasitic resistance and capacitance can approach or even outpace other aspects of transistor performance, such as fringing capacitance or source drain resistance. The total resistance in a device is comprised of two components: internal resistance (which is essentially channel resistance) and external resistance (which is the combination of source drain resistance and metal contact resistance). As key feature sizes shrink at advanced technology nodes, external resistance plays an increasingly important role. Simulation-based design-technology co-optimization (DTCO) offers us some insight into the sensitivity of FinFET device performance to changes in process flows that impact external resistance.

A paper recently presented at the 2019 China Semiconductor Technology International Conference (CSTIC) describes a study of FinFET sensitivity to changes in a silicon germanium epitaxial process, which may impact both capacitance and resistance. The model, built using the integrated process modeling and electrical analysis capabilities of the Coventor SEMulator3D® virtual fabrication platform, studies the resistance and capacitance induced by SiGe epitaxial growth based on varying epi thicknesses.

The simulated gate-last flow process is shown in Figure 1 for a 14nm FinFET case. The front end of line (FEOL) process is composed of several primary unit process steps: self-aligned quadruple patterning (SAQP) lithography and etching to generate the shape of the fins; shallow trench isolation and dummy gate patterning processes to begin the gate-last sequence; and finally, source drain SiGE epitaxial and replacement metal gate deposition complete the fabrication process. The final geometric structure of the modeled device is shown in Figure 2, where gate length is approximately 20nm and the source drain SiGe has a diamond shape.

Figure 1: Main steps of FinFET process flow

Figure 1: Main steps of FinFET process flow

Figure 2: Device structure with metal fill

Figure 2: Device structure with metal fill

Let’s take a closer look at the fabrication process. Figure 3(a) shows the source drain profile prior to any SiGe epi growth. The simulated epitaxial growth profile (3(b-f)) shows increasing thicknesses ranging from 80nm to 120nm as epitaxy growth occurs. The final shape of the source-drain profile is determined by the sum of growth in every direction, meaning that the silicon germanium structure (purple) increases in size as the SiGe thickness increases.

Figure 3: source drain structure without epi and with different epi thicknesses

Figure 3: source drain structure without epi and with different epi thicknesses

Calculated resistance values are based on the various epitaxial-generated shapes, as shown in Figure 3. The model uses simulated electrodes to calculate resistance at the ends of the SiGe epi structure, shown in Figure 4. An obvious transition point occurs at approximately 100nm epi thickness, where resistance decreases sharply—leading to the conclusion that 80nm or 90nm SiGe epi thicknesses are likely insufficient to provide enough contact area for lower resistance.  Yet thicknesses of 110nm and 120nm show another increase in resistance, due to the increase in distance between the top electrode and the bottom electrode. There appears to be an optimal window for SiGe epi thickness at 100 nm, where the lowest SiGe resistance occurs.

Figure 4: Electrode locations for resistance simulation, and SiGe resistance vs. epi thickness simulation results

Figure 4: Electrode locations for resistance simulation, and SiGe resistance vs. epi thickness simulation results

A current-thickness simulation, performed using the SEMulator3D software’s built-in TCAD capabilities, verifies the accuracy of the calculations. Figure 5 shows values of on current that correlate to the resistance values shown in Figure 4, where resistance is plotted against epi thickness.

Figure 5: Electrode locations for current simulation, and on current vs. SiGe epi thickness curve

Figure 5: Electrode locations for current simulation, and on current vs. SiGe epi thickness curve

SiGe thickness variation may also affect capacitance, since greater thickness increases the contact between the SiGe area and the Spacer/High-k feature. The results are shown in Figure 6, where capacitance is shown to have a linear dependence on the epi thickness. (Fringing gate-to-contact capacitance and spacer capacitance are combined to calculate the total capacitance.)

Figure 6: Capacitance components and capacitance variance compared to different epi thicknesses

Figure 6: Capacitance components and capacitance variance compared to different epi thicknesses

There are three stages in epi formation demonstrated by the capacitance curve: initial diamond shape formation, diamond shape growth, and diamond shape saturation, with demonstrated capacitance variation among the stages of epi formation. Capacitance increases very slowly at 80nm and 90nm epi thicknesses. Relative epi thickness increases most quickly when the epi thickness is between 90nm and 100nm, corresponding to a faster increase in capacitance; when the diamond shape is relatively large (above 120 nm), the increase in capacitance slows again.

Read the full paper here for further details about the effect of epitaxial process variations on FinFET device performance.  Other factors, such as doping profile and selection of metal contact resistance would also likely affect resistance and capacitance performance [2][3].

REFERENCES

  1. Kim, M. S., Cane-Wissing, W., Li, X., Sampson, J., Datta, S., Gupta, S. K., & Narayanan, V. (2016). Comparative area and parasitics analysis in FinFET and heterojunction vertical TFET standard cells. ACM Journal on Emerging Technologies in Computing Systems (JETC), 12(4), 38.
  2. Shintri, Shashidhar, et al. “Effects of high in-situ source/drain boron doping in p-FinFETs on physical and device performance characteristics.” Materials Science in Semiconductor Processing 82 (2018): 9-13.
  3. Auth, C., et al. “A 10nm high performance and low-power CMOS technology featuring 3rd generation FinFET transistors, Self-Aligned Quad Patterning, contact over active gate and cobalt local interconnects.” Electron Devices Meeting (IEDM), 2017 IEEE International. IEEE, 2017.
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