The first computers were built using electro-mechanical components, unlike today’s modern electronic systems. Alain Turing’s cryptanalysis multiplier and Konrad Zuse’s Z2 were invented and built in the first half of the 20th century, and were among the first computers ever constructed. Electro-mechanical switches and relays performed logic operations in these machines. Even after computers were first constructed using vacuum-tubes and electronic transistors, some of the earlier electro-mechanical (relay-based) computers remained in service since their slower speed was compensated for by superior reliability. Now, most computers include logic and memory devices that operate using nano-scale, transistor-based technology.
MEMS (Micro-Electro-Mechanical-Systems) are novel miniaturized devices that combine mechanical and electrical functions. These devices are used in mobile phones, automobiles, and many other modern electronic technologies, and have massively changed our lives and the way that we work and live. MEMS are also fabricated on silicon wafers. They use the same or similar manufacturing processes as transistor-based logic and memory chips for deposition, etch and cleaning steps. So, could we use MEMS technology to create computers based on micro-scale electro-mechanical logic and memory, similar to the early days of computing?MEMS products can be directly integrated into conventional complementary metal-oxide-semiconductors (CMOS) logic and memory devices. However, the majority of today’s MEMS products are based on a dual chip approach, where there is one fabrication process for the MEMS device and another process to create the related electronic interface (CMOS) components. Nevertheless, there are a large number of successful examples of MEMS devices being directly produced and integrated with CMOS electronics. Texas Instrument’s DLP mirror-array, Analog Devices surface micromachined accelerometer for automotive airbag applications, and AAC-WiSpry’s RF MEMS switch are a few examples of MEMS devices that have been monolithically integrated on CMOS wafers with great success.
For the past few decades, CMOS electronics have followed Moore’s law by scaling down in size and exponentially increasing transistor density. This scaling process continues as we speak, with more and more complex structures being invented for transistor architectures. One alternative to this transistor architecture is to employ existing CMOS technologies and monolithically integrate miniaturized electro-mechanical switches into logic and memory devices. These miniaturized switches are often referred to as Nano-Electro-Mechanical-Systems (NEMS).
One motivation for developing NEMS- based logic or memory is power consumption. Power consumption has become a major bottleneck in state-of-the-art computer technology. This is particularly an issue for emerging low-energy computing applications, such as autonomous sensor nodes employed in the Internet-of-Things (IoT), wireless communications devices, and novel mobile computers used in edge computing. These applications all require logic circuits with dramatically improved energy efficiency. NEMS-based switches offer practically zero leakage current during the off-state, sharp switching characteristics, and high on-current performance (low resistance in the on-current state). The potential benefits of this technology include an order of magnitude improvement in energy efficiency. Furthermore, electrostatically actuated NEMS have demonstrated that they operate efficiently at low and high temperatures (-150 C to 300 C), allowing them to operate in difficult environmental conditions.NEMS can be fabricated using the metal layers of standard CMOS Back-End-Of-Line (BEOL) interconnection processes. The BEOL processes can be integrated with the Front-End-Of-Line (FEOL) portion of the device. The FEOL section includes the active (transistor) section of the device and includes the main process building block on any computer chip. The BEOL manufactured stack is made up of multiple metal and dielectric layers to form interconnection wires and vias (interconnection structures). With downscaling of electronic devices, the minimum feature size and spacing of these patterned structures (so called pitch) is becoming smaller and smaller, while the number of metal layers is growing. These small feature sizes represent a potential technology challenge but also great opportunity for a new generation of NEMS-based devices. So far, NEMS-based logic circuits have been experimentally demonstrated using 0.35 um, 0,18 um, 65 nm and 16 nm CMOS manufacturing processes.
Figure 2 displays a BEOL NEMS relay designed at Berkeley University using a standard 65nm CMOS process . The switch is electrostatically actuated and consists of a movable beam, two programming electrodes (labeled Program 0 and Program 1) and two contact electrodes (labeled D0 and D1). The switch is shown in plan view (a) and in a cross-sectional view along the cutline a-a’ highlighting the metal/via layers (b). Simulation results in Figure 2 display the position of the NEMS switch when it is programmed to state “0” (c) and state “1” (d). The color scale in (c) and (d) displays the magnitude of displacement due to electrostatic actuation. The simulated transient response (e) displays the program voltage waveforms (upper graph) and the corresponding beam tip position over time (lower graph). Multiple NEMS switches can be placed together in arrays to perform logical or memory functions.
BEOL NEMS switches are able to satisfy design requirements for low power operating voltage, nonvolatility and programmability. Different physical aspects of the NEMS design need to be addressed in order to optimize device performance. Available design parameters for a NEMS-based switch include the beam length, thickness, and width of the beam, as well as the actuation contact gap and contact area. Some of these parameters can be chosen by the designer, others depend upon the fabrication technology and scale down with each new process generation. Using a predictive model in MEMS+®, the minimum program voltage can be calculated for optimized designs at different technology nodes. A smaller voltage and electrode capacitance will decrease program energy. The mechanical program delay will diminish with scaling since the contact gap requires smaller beam displacement, and the reduced mass of the beam leads to faster electrostatic actuation. With each new node of CMOS technology, the minimum feature size is reduced, enabling smaller gaps. Therefore, the density, switching energy and switching delay of BEOL NEMS switches are expected to improve with technology scaling [4, 5].
Several research groups have come up with different designs for miniaturized electro-mechanical devices that can be used in logic and memory applications. These designs include meander-shaped suspensions , different configurations for lateral or vertical electrodes [7, 8] and resonator-based programmable logic gates . Many semiconductor engineers remember Feynman’s famous lecture where he suggested that we explore the “room at the bottom”  of physical manipulation by downscaling transistor architectures to nanoscale dimensions. Today, this is happening with present day FEOL semiconductor processing. We should not forget that there are also tremendous opportunities to explore “room at the top” at the BEOL portion of semiconductor devices. For certain specialized, low power applications, NEMS-based devices could be highly valuable during logic and memory development, due to their energy efficiency and ability to operate in adverse environments. NEMS-based architectures might bring us back to the earliest days of electro-mechanical computing, but do so using silicon-based devices in low-power computing applications.