IMEC Partner Technical Week Review
By: Aurélie Juncker, Semiconductor Process & Integration Engineer
a. Fully aligned Via with Cu recess approach – Gayle Murdoch, b. STT-RAM – Davide Crotti, c. N10 Supernova2 process – Matt Gallagher
In March 2016, Coventor was invited to the biannual Partner Technical Week (PTW) at IMEC in Leuven, Belgium. IMEC, a world-leading research group in nanotechnology, organizes their Partner Technical Week every 6 months to present scientific results to their partners. During this week, a number of specialists from IMEC’s many partner companies also discuss their progress in areas related to IMEC’s research. This event brings together a large number of engineers who are specialists in their domain, and provides an interesting forum to leverage the scientific knowledge gained by IMEC and its partners.
Coventor’s virtual fabrication software, SEMulator3D®, is currently used in 4 main groups at IMEC: Logic, Interconnect, Lithography and Memory. IMEC engineers use SEMulator3D to perform calibration of physically predictive simulation decks for advanced technologies such as N7 FEOL and BEOL. Coventor’s collaboration with IMEC’s Logic and Interconnect groups began a few years earlier and has demonstrated excellent results. This year, we had the opportunity to work with IMEC on a project using the new RC extraction capability in SEMulator3D Version 6.0. This project, in partnership with Gayle Murdoch of IMEC, used SEMulator3D to simulate a fully aligned via with a Cu recess. Using SEMulator3D’s new capacitance extraction capabilities, Gayle created a DOE on misalignment with capacitance extraction. Thanks to this simulation, Gayle was able to compare different processes and highlight potential process issues.
In the Memory group, a significant Etch versus CMP variation DOE was performed by the STT-RAM project group, led by Davide Crotti. Davide presented work completed in SEMulator3D to calibrate MTJ etch steps and define specifications of CMP and Etch on a Trench module. The purpose of this experimental design was to mark out the range of variations allowed in the experimental model.
Matt Gallagher, in the Lithography group, made a poster during PTW to highlight SEMulator3D simulation deck validation and its use in IMEC’s N7/N10 platform. SEMulator3D was used to generate approximately 1 million virtual wafers to quantify the impact of different patterning processes and compare different alignment schemes. This process variation experiment analyzed both EUV vs DUV patterning, along with different design structures. As an example, Mark generated 200 random Gaussian values for overlay at the M1 and V0 level and compared different processes such as i193 and EUV. Most of this work was based upon IMEC’s N10 Supernova2 process at the M1 V0 level, but Matt also showed some preliminary results using IMEC’s N7 process.
COVENTOR has also created a method to incorporate OCD metrology equipment measurements into SEMulator3D virtual fabrication experiments through an interface with the NOVA-MARS multi-channel metrology modeling engine. IMEC presented results during the Lithography session at PTW using this interface, where IMEC personnel demonstrated results from a Twin-Peak process modeling simulation. This model, implemented in SEMulator3D, was used to simulate Fin Etch imperfections and generate realistic results highlighting process variability issues.
SEMulator3D is used in a quite a few other projects at IMEC and there is a huge amount of interesting and exciting work happening there. I hope to be able to report on other interesting SEMulator3D simulation work at IMEC in my next PTW blog.
