Toward Smarter Design of Smart Systems
December 3, 2013
Best wishes for the holidays from Coventor
December 24, 2013
At the 2013 edition of the IEDM conference held this month in Washington, DC, some of the brightest minds in the design and manufacture of semiconductors gathered to discuss trends and challenges in the IC industry. One particular session, hosted by Coventor, assembled 5 experts on leading edge process development from some of the biggest chip players in the business: IBM, GlobalFoundries, Samsung, ST Microelectronics and renowned research organization IMEC.
The consensus of this elite group was not surprising: there is no shortage of new and unprecedented challenges standing in the way of continued scaling of IC technology. Each panelist offered their own opinion on what the biggest challenge is, and they ran the gamut of tough tasks.
While there may not have been 100% agreement on which challenge is greatest, it was clear that new approaches, both technically and business-wise, are required to keep things moving along. So it was appropriate that Coventor, which enables a Virtual Fabrication approach to process development, organized and moderated the panel (under the direction of our own Dr. David Fried). Many of the challenges raised can be addressed very effectively with Coventor’s SEMulator3D platform.
We’d like to thank the expert panelists that came together for this insightful discussion, including
• Dr. Brian Green, Senor Engineer/FEOL Architect: IBM
• Dr. Andy Wei, Principle Member of Technical Staff – 10nm: GLOBALFOUNDRIES
• Jaouen Herve, Director, Modeling & Simulation: ST Microelectronics
• Sean Lian, Director/Technology Lead: Samsung
• Laith Altimime, Director CMOS Technology & Design: IMEC
For a full report on the panel, go to EE times coverage.
![Fig. 2. Silicon spin qubit centered in the dotted circle, control and readout signals (M, P, R, T, and Q) are shown in the inset. Simplified schematics of the quantum point contact and corollary circuits are shown. The voltage source is implemented as a digital-to-analog converter at room temperature. (Taken from [6])](https://www.coventor.com/wp-content/uploads/2022/05/Fig.-2.-Silicon-spin-qubit-centered-in-the-dotted-circle-control-and-readout.png)
![Figure 2: Schematic view of standard CMOS including an electro-mechanical switch monolithically integrated into BEOL [2]. Courtesy: University of California, Berkeley](https://www.coventor.com/wp-content/uploads/2022/04/Figure-2-April-2022-MEMS-Blog-for-Coventor-website.png)
