Yesterday Intel announced its readiness for high-volume manufacturing of 3-D tri-gate (FinFET) transistors. Among other benefits, the tri-gate configuration allows Intel to manufacture higher performance fully-depleted devices without resorting to Silicon-On-Insulator (SOI) wafers. The performance gains quoted by Intel over their own 32nm planar transistor technology are impressive, including a 37% speed increase at low voltage , 18% speed increase at high voltage and 50% or greater power reduction at constant performance. All these performance benefits come with only a 2-3% cost increase.
The shift to tri-gate transistors is a major architectural and conceptual shift from standard planar transistors. Due to the non-planar nature of the devices, process integration challenges in producing such a device are considerable. SEMulator3D is well placed to help process integration engineers understand and surmount manufacturing challenges for advanced FinFET devices, as demonstrated with the 32nm FinFET models that are available on our application examples page.
SEMulator3D is used for process development/integration, as well as documentation and communication about complex processes and for technology transfer. More information about how and why to use SEMulator3D can be found on Coventor’s SEMulator3D website.
SEM image and information about Intel transistors are courtesy of Intel Corporation.
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