Overcoming Design and Process Challenges in Next-Generation SRAM Cell Architectures

Static Random-Access Memory (SRAM) has been a key element for logic circuitry since the early age of the semiconductor industry. The SRAM cell usually consists of six transistors connected to each other in order to perform logic storage and other functions. The size of the 6T (6 Transistors) SRAM cell has shrunk steadily over the past decades, thanks to Moore’s law and the size reduction of the transistors along with denser wiring & contacts.

Surprisingly, two things have never changed in SRAM semiconductor manufacturing: placement of the transistors has always been done side-by-side, and carrier (electron and hole) transport has always been performed horizontally. Logic has been stuck in the X-Y plane over the past few decades, without considering the third dimension as a path to an architecture with a smaller footprint.

We can be inspired by NAND technology, which already moved from 2D to 3D a few years back. Let’s imagine a logic cell with flipped (vertical) transistors that are stacked on top of each other. Could this new architecture achieve the smallest record SRAM cell size (with the footprint being reduced to one transistor only)? These are the questions that were asked by the Coventor Semiconductor Process & Integration team at Lam’s Computational Products division a few months earlier, when they looked at the future of SRAM technology.

Figure: Description of the five modules required to build a SSVT-SRAM architecture

The team used the SEMulator3D^® virtual fabrication software to test a very innovative design and process flow for a new SRAM architecture.  This new architecture was named the SSVT (Six Stacked Vertical Transistors)-SRAM cell. The work, presented in February 2021 at the SPIE Advanced Lithography conference, involved pathfinding studies and virtual fabrication of a 0.0093um² SRAM cell.  The publication discusses the design, manufacturing and processing challenges that will need to be overcome to enable adoption of this very competitive architecture.  Some of the more challenging aspects of the technology  included the formation of contact landing zones for the transistor source and drain, the design of “via” contacts for the transistor gate, the ability to process silicon at two levels (for the channel, the source/drain and the gate formations) and the ability to pattern and fill high aspect ratio vias.   This innovative work will help our customers better understand the requirements of next generation logic architectures, and ensure that Coventor is ready to meet the needs of its current and future customers.